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ORCIDRajesh Galivanche
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2010 – 2019
- 2017
[j8]Martin Omaña, Marco Padovani, Kreshnik Veliu, Cecilia Metra, Juergen Alt, Rajesh Galivanche:
New Approaches for Power Binning of High Performance Microprocessors. IEEE Trans. Computers 66(7): 1159-1171 (2017)- [j7]Martin Omaña
, Daniele Rossi, Filippo Fuzzi, Cecilia Metra, Chandra Tirumurti, Rajesh Galivanche:
Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 238-246 (2017) - 2016
- [j6]Martin Omaña, Daniele Rossi, Edda Beniamino, Cecilia Metra, Chandrasekharan Tirumurti, Rajesh Galivanche:
Low-Cost and High-Reduction Approaches for Power Droop during Launch-On-Shift Scan-Based Logic BIST. IEEE Trans. Computers 65(8): 2484-2494 (2016) - 2014
- [c14]Martin Omaña, Daniele Rossi, Edda Beniamino, Cecilia Metra, Chandra Tirumurti, Rajesh Galivanche:
Power droop reduction during Launch-On-Shift scan-based logic BIST. DFT 2014: 21-26 - 2013
- [j5]Daniele Rossi, Martin Omaña, G. Garrammone, Cecilia Metra, Abhijit Jas, Rajesh Galivanche:
Low Cost Concurrent Error Detection Strategy for the Control Logic of High Performance Microprocessors and Its Application to the Instruction Decoder. J. Electron. Test. 29(3): 401-413 (2013) - 2012
- [j4]Michail Maniatakos, Chandrasekharan Tirumurti, Rajesh Galivanche, Yiorgos Makris:
Global Signal Vulnerability (GSV) Analysis for Selective State Element Hardening in Modern Microprocessors. IEEE Trans. Computers 61(10): 1361-1370 (2012) - 2011
- [j3]Cecilia Metra, Rajesh Galivanche:
Guest Editors' Introduction: Special Section on Concurrent On-Line Testing and Error/Fault Resilience of Digital Systems. IEEE Trans. Computers 60(9): 1217-1218 (2011) - 2010
- [c13]Daniele Rossi, Martin Omaña, Gianluca Berghella, Cecilia Metra, Abhijit Jas, Chandra Tirumurti, Rajesh Galivanche:
Low cost and low intrusive approach to test on-line the scheduler of high performance microprocessors. Conf. Computing Frontiers 2010: 113-114 - [c12]Amir Nahir, Avi Ziv, Rajesh Galivanche, Alan J. Hu, Miron Abramovici, Albert Camilleri, Bob Bentley, Harry Foster, Valeria Bertacco, Shakti Kapoor:
Bridging pre-silicon verification and post-silicon validation. DAC 2010: 94-95 - [c11]Suriyaprakash Natarajan, Arun Krishnamachary, Eli Chiprout, Rajesh Galivanche:
Path coverage based functional test generation for processor marginality validation. ITC 2010: 544-552
2000 – 2009
- 2009
- [j2]Gadi Singer, Rajesh Galivanche, Srinivas Patil, Mike Tripp:
The Challenges of Nanotechnology and Gigacomplexity. IEEE Des. Test Comput. 26(1): 88-93 (2009) - 2008
- [c10]Ramtilak Vemu, Abhijit Jas, Jacob A. Abraham, Srinivas Patil, Rajesh Galivanche:
A low-cost concurrent error detection technique for processor control logic. DATE 2008: 897-902 - [c9]Cecilia Metra, Daniele Rossi, Martin Omaña, Abhijit Jas, Rajesh Galivanche:
Function-Inherent Code Checking: A New Low Cost On-Line Testing Approach for High Performance Microprocessor Control Logic. ETS 2008: 171-176 - 2007
- [c8]Anis Uzzaman, Fidel Muradali, Takashi Aikyo, Robert C. Aitken, Tom Jackson, Rajesh Galivanche, Takeshi Onodera:
Test Roles in Diagnosis and Silicon Debug. ATS 2007: 367 - [c7]Rajesh Galivanche, Rohit Kapur, Antonio Rubio:
Testing in the year 2020. DATE 2007: 960-965 - 2006
- [c6]Rajesh Galivanche, Bob Gottlieb:
Session Abstract. VTS 2006: 422-423 - 2005
- [c5]Rajesh Galivanche:
Is the concern for soft-error overblown? ITC 2005: 1269 - 2004
- [c4]Sandip Kundu, T. M. Mak, Rajesh Galivanche:
Trends in manufacturing test methods and their implications. ITC 2004: 679-687 - 2003
- [c3]Bill Grundmann, Rajesh Galivanche, Sandip Kundu:
Circuit and Platform Design Challenges in Technologies beyond 90nm. DATE 2003: 10044-10049 - 2001
- [j1]Sandip Kundu, Sujit T. Zachariah, Sanjay Sengupta, Rajesh Galivanche:
Test Challenges in Nanometer Technologies. J. Electron. Test. 17(3-4): 209-218 (2001) - 2000
- [c2]Sandip Kundu, Sanjay Sengupta, Rajesh Galivanche:
Test challenges in nanometer technologies. ETW 2000: 83-90
1980 – 1989
- 1989
- [c1]Dick L. Liu, Rajesh Galivanche, Charlie C. Hsu:
An automatic test pattern generation program for large ASICs. ICCD 1989: 244-248
Coauthor Index
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