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2020 – today
- 2022
[c8]Tessil Thomas, Bharath Venkatasubramanian, Dinesh Sthapit, Christopher Gray, Atresh Gummadavelly, Janick Bergeron, Pankaj Mehta, Prabu Thangamuthu:
Left-shifter: A pre-silicon framework for usage model based performance verification of the PCIe interface in server processor system on chips. ISPASS 2022: 90-98
2000 – 2009
- 2008
- [c7]Janick Bergeron:
Advances in low power verification. ISLPED 2008: 327-328 - 2007
- [c6]Sunil Kakkar, Janick Bergeron, Brian Bailey, Harry Foster, Ian Harris:
Panel: Unified approach leading to a seamlessly evolving test bench for all phases of a multi-core design, validation and production test. HLDVT 2007: 167-168 - 2006
- [c5]Janick Bergeron, Harry Foster, Andrew Piziali, Raj Shekher Mitra, Catherine Ahlschlager, Doron Stein:
Building a verification test plan: trading brute force for finesse. DAC 2006: 805-806 - 2005
- [c4]Francine Bacchini, Gabe Moretti, Harry Foster, Janick Bergeron, Masayuki Nakamura, Shrenik Mehta, Laurent Ducousso:
Is methodology the highway out of verification hell? DAC 2005: 521-522 - [c3]Janick Bergeron:
Modeling Usable and Reusable Transactors in System Verilog. VLSI Design 2005: 36- - 2001
- [c2]Gabe Moretti, Tim Hopes, Ramesh Narayanaswamy, Nanette Collins, Dave Kelf, Tom Anderson, Janick Bergeron, Ashish Dixit, Peter Flake:
Panel: Your Core - My Problem? Integration and Verification of IP. DAC 2001: 170-171
1990 – 1999
- 1995
- [c1]Allan Silburt, Ian Perryman, Janick Bergeron, Stacy Nichols, Mario Dufresne, Greg Ward:
Accelerating Concurrent Hardware Design with Behavioural Modelling and System Simulation. DAC 1995: 528-533
Coauthor Index
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