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2020 – today
- 2020
[j1]Peter Flake, Phil Moorby, Steve Golson, Arturo Salz, Simon J. Davidmann:
Verilog HDL and its ancestors and descendants. Proc. ACM Program. Lang. 4(HOPL): 87:1-87:90 (2020)
2010 – 2019
- 2013
- [c8]Peter Flake:
Why SystemVeriog? FDL 2013: 1-6 - [c7]Peter Flake, Frank Oppenheimer:
Systemc infrastructure and extensions. FDL 2013: 1
2000 – 2009
- 2006
- [c6]Peter Flake, Simon J. Davidmann, Frank Schirrmeister:
System-level exploration tools for MPSoC designs. DAC 2006: 286-287 - 2004
- [c5]Donatella Sciuto
, Grant Martin, Wolfgang Rosenstiel, Stuart Swan, Frank Ghenassia, Peter Flake, Johny Srouji:
SystemC and SystemVerilog: Where do They Fit? Where are They Going? DATE 2004: 122-129 - 2001
- [c4]Gabe Moretti, Tim Hopes, Ramesh Narayanaswamy, Nanette Collins, Dave Kelf, Tom Anderson, Janick Bergeron, Ashish Dixit, Peter Flake:
Panel: Your Core - My Problem? Integration and Verification of IP. DAC 2001: 170-171 - 2000
- [c3]Peter Flake, Simon J. Davidmann:
Superlog, a unified design language for system-on-chip. ASP-DAC 2000: 583-586 - [c2]Masaharu Imai, Gary Smith, Steven Schulz, Karen Bartleson, Daniel Gajski, Wolfgang Rosenstiel, Peter Flake, Hiroto Yasuura:
One language or more?: how can we design an SoC at a system level? ASP-DAC 2000: 653-654
1980 – 1989
- 1983
- [c1]Peter Flake, Philip Moorby, Gerry Musgrave:
An algebra for logic strength simulation. DAC 1983: 615-618
Coauthor Index
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