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ORCIDYosinori Watanabe
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2010 – 2019
- 2017
[p3]Grant Martin, Frank Schirrmeister, Yosinori Watanabe:
Hardware/Software Codesign Across Many Cadence Technologies. Handbook of Hardware/Software Codesign 2017: 1093-1126- 2013
- [c42]Alex Kondratyev, Luciano Lavagno, Mike Meyer, Yosinori Watanabe:
Share with care: a quantitative evaluation of sharing approaches in high-level synthesis. DATE 2013: 1547-1552 - 2012
- [c41]Alex Kondratyev, Luciano Lavagno, Mike Meyer, Yosinori Watanabe:
Exploiting area/delay tradeoffs in high-level synthesis. DATE 2012: 1024-1029 - [c40]Yosinori Watanabe, Stuart Swan:
Clearing the clutter: Unified modeling and verification methodology for system level hardware design. MEMOCODE 2012: 21-23 - 2011
- [c39]Alex Kondratyev, Luciano Lavagno, Mike Meyer, Yosinori Watanabe:
Realistic performance-constrained pipelining in high-level synthesis. DATE 2011: 1382-1387 - 2010
- [j13]Gianpiero Cabodi, Luciano Lavagno, Marco Murciano, Alex Kondratyev, Yosinori Watanabe:
Speeding-up heuristic allocation, scheduling and binding with SAT-based abstraction/refinement techniques. ACM Trans. Design Autom. Electr. Syst. 15(2): 12:1-12:34 (2010) - [c38]Luciano Lavagno, Alex Kondratyev, Yosinori Watanabe, Qiang Zhu, Mototsugu Fujii, Mitsuru Tatesawa, Noriyasu Nakayama:
Incremental high-level synthesis. ASP-DAC 2010: 701-706
2000 – 2009
- 2009
- [j12]Eric Cheung, Xi Chen, Harry Hsieh, Abhijit Davare, Alberto L. Sangiovanni-Vincentelli
, Yosinori Watanabe:
Runtime deadlock analysis for system level design. Des. Autom. Embed. Syst. 13(4): 287-310 (2009) - [c37]Yosinori Watanabe:
Examining Important Corner Cases: Verification of Interacting Architectural Components in System Designs. ACSD 2009: 19 - 2008
- [j11]Cong Liu, Alex Kondratyev, Yosinori Watanabe, Jörg Desel, Alberto L. Sangiovanni-Vincentelli:
Schedulability Analysis of Petri Nets Based on Structural Properties. Fundam. Informaticae 86(3): 325-341 (2008) - 2006
- [c36]Cong Liu, Alex Kondratyev, Yosinori Watanabe, Alberto L. Sangiovanni-Vincentelli, Jörg Desel:
Schedulability Analysis of Petri Nets Based on Structural Properties. ACSD 2006: 69-78 - [c35]Shinjiro Kakita, Yosinori Watanabe, Douglas Densmore, Abhijit Davare, Alberto L. Sangiovanni-Vincentelli:
Functional Model Exploration for Multimedia Applications via Algebraic Operators. ACSD 2006: 229-238 - 2005
- [j10]Gianpiero Cabodi, Alex Kondratyev, Luciano Lavagno, Sergio Nocco, Stefano Quer, Yosinori Watanabe:
A BMC-based formulation for the scheduling problem of hardware systems. Int. J. Softw. Tools Technol. Transf. 7(2): 102-117 (2005) - [j9]Yajun Ran, Alex Kondratyev, Kenneth H. Tseng, Yosinori Watanabe, Malgorzata Marek-Sadowska:
Eliminating false positives in crosstalk noise analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(9): 1406-1419 (2005) - [j8]Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Claudio Passerone, Yosinori Watanabe:
Quasi-static scheduling of independent tasks for reactive systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(10): 1492-1514 (2005) - [c34]Xi Chen, Abhijit Davare, Harry Hsieh, Alberto L. Sangiovanni-Vincentelli, Yosinori Watanabe:
Simulation based deadlock analysis for system level designs. DAC 2005: 260-265 - [c33]Luciano Lavagno, Claudio Passerone, Vishal Shah, Yosinori Watanabe:
A Time Slice Based Scheduler Model for System Level Design. DATE 2005: 378-383 - [c32]Cong Liu, Alex Kondratyev, Yosinori Watanabe, Alberto L. Sangiovanni-Vincentelli:
A structural approach to quasi-static schedulability analysis of communicating concurrent programs. EMSOFT 2005: 10-16 - [r1]Luciano Lavagno, Claudio Passerone, Alex Kondratyev, Yosinori Watanabe:
Quasi-Static Scheduling of Concurrent Specifications. Embedded Systems Handbook 2005 - 2004
- [j7]Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Alexander Taubin, Yosinori Watanabe:
Quasi-static Scheduling for Concurrent Architectures. Fundam. Informaticae 62(2): 171-196 (2004) - [j6]Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe:
Logic of constraints: a quantitative performance and functional constraint formalism. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(8): 1243-1255 (2004) - [c31]Yajun Ran, Alex Kondratyev, Yosinori Watanabe, Malgorzata Marek-Sadowska:
Eliminating False Positives in Crosstalk Noise Analysis. DATE 2004: 1192-1197 - [c30]Guang Yang, Alberto L. Sangiovanni-Vincentelli, Yosinori Watanabe, Felice Balarin:
Separation of concerns: overhead in modeling and efficient simulation techniques. EMSOFT 2004: 44-53 - 2003
- [j5]Felice Balarin, Yosinori Watanabe, Harry Hsieh, Luciano Lavagno, Claudio Passerone, Alberto L. Sangiovanni-Vincentelli:
Metropolis: An Integrated Electronic System Design Environment. Computer 36(4): 45-52 (2003) - [j4]Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe:
Formal Verification for Embedded System Designs. Des. Autom. Embed. Syst. 8(2-3): 139-153 (2003) - [c29]Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe:
Case Studies of Model Checking for Embedded System Designs. ACSD 2003: 20-28 - [c28]Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Yosinori Watanabe:
Quasi-Static Scheduling for Concurrent Architectures. ACSD 2003: 29-40 - [c27]Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe:
Automatic trace analysis for logic of constraints. DAC 2003: 460-465 - [c26]Bo Hu, Yosinori Watanabe, Alex Kondratyev, Malgorzata Marek-Sadowska:
Gain-based technology mapping for discrete-size cell libraries. DAC 2003: 574-579 - [c25]Donald Chai, Alex Kondratyev, Yajun Ran, Kenneth H. Tseng, Yosinori Watanabe, Malgorzata Marek-Sadowska:
Temporofunctional crosstalk noise analysis. DAC 2003: 860-863 - [c24]Antonio G. Lomeña, Marisa Luisa López-Vallejo, Yosinori Watanabe, Alex Kondratyev:
An Efficient Hash Table Based Approach to Avoid State Space Explosion in History Driven Quasi-Static Scheduling. DATE 2003: 10428-10435 - [c23]Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe:
Automatic Generation of Simulation Monitors from Quantitative Constraint Formula. DATE 2003: 11174-11175 - [c22]Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe:
Verifying LOC based functional and performance constraints. HLDVT 2003: 83-88 - [c21]Gianpiero Cabodi, Sergio Nocco, Stefano Quer, Alex Kondratyev, Luciano Lavagno, Yosinori Watanabe:
A BMC-formulation for the scheduling problem in highly constrained hardware Systems. BMC@CAV 2003: 623-638 - [p2]Antonio G. Lomeña, Marisa López-Vallejo, Yosinori Watanabe, Alex Kondratyev:
State Space Compression in History Driven Quasi-Static Scheduling. Embedded Software for SoC 2003: 261-274 - [p1]Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe:
Simulation Trace Verification for Quantitative Constraints. Embedded Software for SoC 2003: 275-285 - 2002
- [c20]Felice Balarin, Luciano Lavagno, Claudio Passerone, Alberto L. Sangiovanni-Vincentelli, Marco Sgroi, Yosinori Watanabe:
Modeling and Designing Heterogeneous Systems. Concurrency and Hardware Design 2002: 228-273 - [c19]Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Claudio Passerone, Yosinori Watanabe:
Quasi-Static Scheduling of Independent Tasksfor Reactive Systems. ICATPN 2002: 80-100 - [c18]Felice Balarin, Luciano Lavagno, Claudio Passerone, Alberto L. Sangiovanni-Vincentelli, Yosinori Watanabe, Guang Yang:
Concurrent execution semantics and sequential simulation algorithms for the metropolis meta-model. CODES 2002: 13-18 - [c17]G. Arrigoni, L. Duchini, Claudio Passerone, Luciano Lavagno, Yosinori Watanabe:
False Path Elimination in Quasi-Static Scheduling. DATE 2002: 964-970 - [c16]Felice Balarin, Luciano Lavagno, Claudio Passerone, Yosinori Watanabe:
Processes, Interfaces and Platforms. Embedded Software Modeling in Metropolis. EMSOFT 2002: 407-416 - [c15]Xi Chen, Fang Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe:
Formal verification of embedded system designs at multiple levels of abstraction. HLDVT 2002: 125-130 - 2001
- [c14]Claudio Passerone, Yosinori Watanabe, Luciano Lavagno:
Generation of minimal size code for scheduling graphs. DATE 2001: 668-673 - [c13]Felice Balarin, Jerry R. Burch, Luciano Lavagno, Yosinori Watanabe, Roberto Passerone, Alberto L. Sangiovanni-Vincentelli:
Constraints specification at higher levels of abstraction. HLDVT 2001: 129-133 - 2000
- [c12]Dirk-Jan Jongeneel, Yosinori Watanabe, Robert K. Brayton, Ralph H. J. M. Otten:
Area and search space control for technology mapping. DAC 2000: 86-91 - [c11]Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Marc Massot, Sandra Moral, Claudio Passerone, Yosinori Watanabe, Alberto L. Sangiovanni-Vincentelli:
Task generation and compile-time scheduling for mixed data-control embedded software. DAC 2000: 489-494
1990 – 1999
- 1999
- [c10]Marco Sgroi, Luciano Lavagno, Yosinori Watanabe, Alberto L. Sangiovanni-Vincentelli:
Quasi-Static Scheduling of Embedded Software Using Equal Conflict Nets. ICATPN 1999: 208-227 - [c9]H. J. H. N. Kenter, Claudio Passerone, W. J. M. Smits, Yosinori Watanabe, Alberto L. Sangiovanni-Vincentelli:
Designing digital video systems: modeling and scheduling. CODES 1999: 64-68 - 1997
- [j3]Eric Lehman, Yosinori Watanabe, Joel Grodstein, Heather Harkness:
Logic decomposition during technology mapping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(8): 813-834 (1997) - 1996
- [j2]Yosinori Watanabe, Lisa M. Guerra, Robert K. Brayton:
Permissible functions for multioutput components in combinational logic optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(7): 732-744 (1996) - 1995
- [c8]Eric Lehman, Yosinori Watanabe, Joel Grodstein, Heather Harkness:
Logic decomposition during technology mapping. ICCAD 1995: 264-271 - [c7]Joel Grodstein, Eric Lehman, Heather Harkness, Bill Grundmann, Yosinori Watanabe:
A delay model for logic synthesis of continuously-sized networks. ICCAD 1995: 458-462 - 1994
- [c6]Yosinori Watanabe, Robert K. Brayton:
State Minimization of Pseudo Non-Deterministic FSM's. EDAC-ETC-EUROASIC 1994: 184-191 - 1993
- [j1]Yosinori Watanabe, Robert K. Brayton:
Heuristic minimization of multiple-valued relations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(10): 1458-1472 (1993) - [c5]Yosinori Watanabe, Robert K. Brayton:
The maximum set of permissible behaviors for FSM networks. ICCAD 1993: 316-320 - [c4]Yosinori Watanabe, Lisa M. Guerra, Robert K. Brayton:
Logic Optimization with Multi-Output Gates. ICCD 1993: 416-420 - [c3]Vigyan Singhal, Yosinori Watanabe, Robert K. Brayton:
Heuristic Minimization of Synchronous Relations. ICCD 1993: 428-433 - 1991
- [c2]Yosinori Watanabe, Robert K. Brayton:
Heuristic Minimazation of Multiple-Valued Relations. ICCAD 1991: 126-129 - [c1]Yosinori Watanabe, Robert K. Brayton:
Incremental Synthesis for Engineering Changes. ICCD 1991: 40-43
Coauthor Index
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