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ORCIDJerry R. Burch
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2000 – 2009
- 2007
[j8]Roberto Passerone
, Jerry R. Burch, Alberto L. Sangiovanni-Vincentelli:
Refinement preserving approximations for the design and verification of heterogeneous systems. Formal Methods Syst. Des. 31(1): 1-33 (2007)- [c27]Alfred Kölbl, Jerry R. Burch, Carl Pixley:
Memory Modeling in ESL-RTL Equivalence Checking. DAC 2007: 205-209 - 2006
- [j7]Alan Mishchenko, Jin S. Zhang, Subarnarekha Sinha, Jerry R. Burch, Robert K. Brayton, Malgorzata Chrzanowska-Jeske:
Using simulation and satisfiability to compute flexibilities in Boolean networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(5): 743-755 (2006) - [j6]Jin S. Zhang, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Jerry R. Burch:
Linear cofactor relationships in Boolean functions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(6): 1011-1023 (2006) - 2005
- [c26]Jin S. Zhang, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Jerry R. Burch:
Detecting support-reducing bound sets using two-cofactor symmetries. ASP-DAC 2005: 266-271 - 2004
- [c25]Roberto Passerone, Jerry R. Burch, Alberto L. Sangiovanni-Vincentelli:
Conservative approximations for heterogeneous design. EMSOFT 2004: 155-164 - 2001
- [c24]Jerry R. Burch, Roberto Passerone, Alberto L. Sangiovanni-Vincentelli:
Overcoming Heterophobia: Modeling Concurrency in Heterogeneous Systems. ACSD 2001: 13- - [c23]Jerry R. Burch, Roberto Passerone, Alberto L. Sangiovanni-Vincentelli:
Using Multiple Levels of Abstractions in Embedded Software Design. EMSOFT 2001: 324-343 - [c22]Felice Balarin, Jerry R. Burch, Luciano Lavagno, Yosinori Watanabe, Roberto Passerone, Alberto L. Sangiovanni-Vincentelli:
Constraints specification at higher levels of abstraction. HLDVT 2001: 129-133 - 2000
- [j5]Youpyo Hong, Peter A. Beerel, Jerry R. Burch, Kenneth L. McMillan:
Sibling-substitution-based BDD minimization using don't cares. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(1): 44-55 (2000)
1990 – 1999
- 1998
- [j4]Peter A. Beerel, Jerry R. Burch, Teresa H. Meng:
Checking Combinational Equivalence of Speed-Independent Circuits. Formal Methods Syst. Des. 13(1): 37-85 (1998) - [c21]Jerry R. Burch, Vigyan Singhal:
Robust latch mapping for combinational equivalence checking. ICCAD 1998: 563-569 - [c20]Jerry R. Burch, Vigyan Singhal:
Tight integration of combinational verification methods. ICCAD 1998: 570-576 - 1997
- [c19]Youpyo Hong, Peter A. Beerel, Jerry R. Burch, Kenneth L. McMillan:
Safe BDD Minimization Using Don't Cares. DAC 1997: 208-213 - 1996
- [c18]Jerry R. Burch:
Techniques for Verifying Superscalar Microprocessors. DAC 1996: 552-557 - [c17]Phillip J. Windley, Jerry R. Burch:
Mechanically Checking a Lemma Used in an Automatic Verification Tool. FMCAD 1996: 362-376 - 1995
- [c16]Robert B. Jones, David L. Dill, Jerry R. Burch:
Efficient validity checking for processor verification. ICCAD 1995: 2-6 - 1994
- [j3]Jerry R. Burch, Edmund M. Clarke, David E. Long, Kenneth L. McMillan, David L. Dill:
Symbolic model checking for sequential circuit verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(4): 401-424 (1994) - [c15]Peter A. Beerel, Jerry R. Burch, Teresa H.-Y. Meng:
Sufficient conditions for correct gate-level speed-independent circuits. ASYNC 1994: 33-43 - [c14]Jerry R. Burch, David L. Dill:
Automatic verification of Pipelined Microprocessor Control. CAV 1994: 68-80 - 1993
- [c13]Peter A. Beerel, Jerry R. Burch, Teresa H.-Y. Meng:
Efficient verification of determinate speed-independent circuits. ICCAD 1993: 261-267 - [c12]Jerry R. Burch, David L. Dill, Elizabeth Wolf, Giovanni De Micheli:
Modeling hierarchical combinational circuits. ICCAD 1993: 612-617 - 1992
- [j2]Jerry R. Burch, Edmund M. Clarke, Kenneth L. McMillan, David L. Dill, L. J. Hwang:
Symbolic Model Checking: 10^20 States and Beyond. Inf. Comput. 98(2): 142-170 (1992) - [c11]Jerry R. Burch, David E. Long:
Efficient Boolean function matching. ICCAD 1992: 408-411 - [c10]Jerry R. Burch:
Delay Models for Verifying Speed-Dependent Asynchronous Circuits. ICCD 1992: 270-274 - 1991
- [c9]Jerry R. Burch, Edmund M. Clarke, David E. Long:
Representing Circuits More Efficiently in Symbolic Model Checking. DAC 1991: 403-407 - [c8]Jerry R. Burch:
Using BDDs to Verify Multipliers. DAC 1991: 408-412 - [c7]Jerry R. Burch, Edmund M. Clarke, David E. Long:
Symbolic Model Checking with Partitioned Transistion Relations. VLSI 1991: 49-58 - 1990
- [c6]Jerry R. Burch:
Verifying Liveness Properties by Verifying Safety Properties. CAV 1990: 224-232 - [c5]Jerry R. Burch, Edmund M. Clarke, Kenneth L. McMillan, David L. Dill:
Sequential Circuit Verification Using Symbolic Model Checking. DAC 1990: 46-51 - [c4]Jerry R. Burch:
Verifying Liveness Properties by Verifying Safety Properties. CAV (DIMACS/AMS volume) 1990: 93-102 - [c3]Jerry R. Burch, Edmund M. Clarke, Kenneth L. McMillan, David L. Dill, L. J. Hwang:
Symbolic Model Checking: 10^20 States and Beyond. LICS 1990: 428-439
1980 – 1989
- 1989
- [c2]Jerry R. Burch:
Combining CTL, Trace Theory and Timing Models. Automatic Verification Methods for Finite State Systems 1989: 334-348 - [c1]Jerry R. Burch:
Modeling timing assumptions with trace theory. ICCD 1989: 208-211 - 1985
- [j1]Alain J. Martin, Jerry R. Burch:
Fair Mutual Exclusion with Unfair P and V Operations. Inf. Process. Lett. 21(2): 97-100 (1985)
Coauthor Index
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