"Fast and accurate estimation of floorplans in logic/high-level synthesis."

Kia Bazargan, Abhishek Ranjan, Majid Sarrafzadeh (2000)

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DOI: 10.1145/330855.330990

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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Kia Bazargan, Abhishek Ranjan, Majid Sarrafzadeh:
Fast and accurate estimation of floorplans in logic/high-level synthesis. ACM Great Lakes Symposium on VLSI 2000: 95-100

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