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2010 – 2019
- 2019
[j9]Pai-Yu Chen
, Shimeng Yu:
Technological Benchmark of Analog Synaptic Devices for Neuroinspired Architectures. IEEE Des. Test 36(3): 31-38 (2019)- 2018
- [j8]Lixue Xia, Boxun Li, Tianqi Tang, Peng Gu, Pai-Yu Chen, Shimeng Yu, Yu Cao, Yu Wang, Yuan Xie, Huazhong Yang:
MNSIM: Simulation Platform for Memristor-Based Neuromorphic Computing System. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(5): 1009-1022 (2018) - [j7]Pai-Yu Chen, Xiaochen Peng, Shimeng Yu:
NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(12): 3067-3080 (2018) - [j6]Rui Liu, Pai-Yu Chen, Xiaochen Peng, Shimeng Yu:
X-Point PUF: Exploiting Sneak Paths for a Strong Physical Unclonable Function Design. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(10): 3459-3468 (2018) - [c16]Xiaoyu Sun, Xiaochen Peng, Pai-Yu Chen, Rui Liu, Jae-sun Seo, Shimeng Yu:
Fully parallel RRAM synaptic array for implementing binary neural network with (+1, -1) weights and (+1, 0) neurons. ASP-DAC 2018: 574-579 - [c15]Pai-Yu Chen, Shimeng Yu:
Reliability perspective of resistive synaptic devices on the neuromorphic system performance. IRPS 2018: 5 - [c14]Win-San Khwa, Jia-Jing Chen, Jia-Fang Li, Xin Si, En-Yu Yang, Xiaoyu Sun, Rui Liu, Pai-Yu Chen, Qiang Li, Shimeng Yu, Meng-Fan Chang:
A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors. ISSCC 2018: 496-498 - 2017
- [j5]Wenchao Qian, Pai-Yu Chen, Robert Karam, Ligang Gao, Swarup Bhunia, Shimeng Yu:
Energy-Efficient Adaptive Computing With Multifunctional Memory. IEEE Trans. Circuits Syst. II Express Briefs 64-II(2): 191-195 (2017) - [j4]Manqing Mao, Pai-Yu Chen, Shimeng Yu, Chaitali Chakrabarti:
A Multilayer Approach to Designing Energy-Efficient and Reliable ReRAM Cross-Point Array System. IEEE Trans. Very Large Scale Integr. Syst. 25(5): 1611-1621 (2017) - [c13]Rui Liu, Pai-Yu Chen, Shimeng Yu:
Design and optimization of a strong PUF exploiting sneak paths in resistive cross-point array. ISCAS 2017: 1-4 - 2016
- [j3]Pai-Yu Chen, Ligang Gao, Shimeng Yu:
Design of Resistive Synaptic Array for Implementing On-Chip Sparse Learning. IEEE Trans. Multi Scale Comput. Syst. 2(4): 257-264 (2016) - [j2]Pai-Yu Chen, Zhiwei Li, Shimeng Yu:
Design Tradeoffs of Vertical RRAM-Based 3-D Cross-Point Array. IEEE Trans. Very Large Scale Integr. Syst. 24(12): 3460-3467 (2016) - [c12]Lixue Xia, Boxun Li, Tianqi Tang, Peng Gu, Xiling Yin, Wenqin Huangfu, Pai-Yu Chen, Shimeng Yu, Yu Cao, Yu Wang, Yuan Xie, Huazhong Yang:
MNSIM: Simulation platform for memristor-based neuromorphic computing system. DATE 2016: 469-474 - [c11]Robert Karam, Rui Liu, Pai-Yu Chen, Shimeng Yu, Swarup Bhunia:
Security Primitive Design with Nanoscale Devices: A Case Study with Resistive RAM. ACM Great Lakes Symposium on VLSI 2016: 299-304 - [c10]Pai-Yu Chen, Jae-sun Seo, Yu Cao, Shimeng Yu:
Compact oscillation neuron exploiting metal-insulator-transition for neuromorphic computing. ICCAD 2016: 15 - [c9]Pai-Yu Chen, Shimeng Yu:
Partition SRAM and RRAM based synaptic arrays for neuro-inspired computing. ISCAS 2016: 2310-2313 - [c8]Ayush Shrivastava, Pai-Yu Chen, Yu Cao, Shimeng Yu, Chaitali Chakrabarti:
Design of a reliable RRAM-based PUF for compact hardware security primitives. ISCAS 2016: 2326-2329 - 2015
- [j1]Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Pai-Yu Chen, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Shimeng Yu, Yu Cao, Jae-sun Seo:
Parallel Architecture With Resistive Crosspoint Array for Dictionary Learning Acceleration. IEEE J. Emerg. Sel. Topics Circuits Syst. 5(2): 194-204 (2015) - [c7]Pai-Yu Chen, Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao, Shimeng Yu:
Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip. DATE 2015: 854-859 - [c6]Pai-Yu Chen, Runchen Fang, Rui Liu, Chaitali Chakrabarti, Yu Cao, Shimeng Yu:
Exploiting resistive cross-point array for compact design of physical unclonable function. HOST 2015: 26-31 - [c5]Pai-Yu Chen, Binbin Lin, I-Ting Wang, Tuo-Hung Hou, Jieping Ye, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao, Shimeng Yu:
Mitigating Effects of Non-ideal Synaptic Device Characteristics for On-chip Learning. ICCAD 2015: 194-199 - [c4]Scott Zuloaga, Rui Liu, Pai-Yu Chen, Shimeng Yu:
Scaling 2-layer RRAM cross-point array towards 10 nm node: A device-circuit co-design. ISCAS 2015: 193-196 - 2014
- [c3]Zihan Xu, Abinash Mohanty, Pai-Yu Chen, Deepak Kadetotad, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Shimeng Yu, Jae-sun Seo, Yu Cao:
Parallel Programming of Resistive Cross-point Array for Synaptic Plasticity. BICA 2014: 126-133 - [c2]Deepak Kadetotad, Zihan Xu, Abinash Mohanty, Pai-Yu Chen, Binbin Lin, Jieping Ye, Sarma B. K. Vrudhula, Shimeng Yu, Yu Cao, Jae-sun Seo:
Neurophysics-inspired parallel architecture with resistive crosspoint array for dictionary learning. BioCAS 2014: 536-539 - [c1]Cong Xu, Pai-Yu Chen, Dimin Niu, Yang Zheng, Shimeng Yu, Yuan Xie:
Architecting 3D vertical resistive memory for next-generation storage systems. ICCAD 2014: 55-62
Coauthor Index
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