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ORCIDJunhyung Um
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2010 – 2019
- 2016
[j5]Subhendu Roy, Derong Liu, Jagmohan Singh, Junhyung Um, David Z. Pan:
OSFA: A New Paradigm of Aging Aware Gate-Sizing for Power/Performance Optimizations Under Multiple Operating Conditions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(10): 1618-1629 (2016)- 2015
- [c10]Subhendu Roy, Derong Liu, Junhyung Um, David Z. Pan:
OSFA: a new paradigm of gate-sizing for power/performance optimizations under multiple operating conditions. DAC 2015: 129:1-129:6
2000 – 2009
- 2009
- [c9]Woo-Cheol Kwon, Sungjoo Yoo, Junhyung Um, Seh-Woong Jeong:
In-network reorder buffer to improve overall NoC performance while resolving the in-order requirement problem. DATE 2009: 1058-1063 - 2006
- [j4]Junhyung Um, Taewhan Kim:
Resource Sharing Combined with Layout Effects in High-Level Synthesis. J. VLSI Signal Process. 44(3): 231-243 (2006) - [c8]Junhyung Um, Woo-Cheol Kwon, Sungpack Hong, Young-Taek Kim, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo, Taewhan Kim:
A systematic IP and bus subsystem modeling for platform-based system design. DATE 2006: 560-564 - 2003
- [j3]Junhyung Um, Taewhan Kim:
Synthesis of arithmetic circuits considering layout effects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(11): 1487-1503 (2003) - [c7]Junhyung Um, Taewhan Kim:
Code Placement with Selective Cache Activity Minimization for Embedded Real-time Software Design. ICCAD 2003: 197-200 - [c6]Junhyung Um, Sangwoo Lee, Youngsoo Park, Sungik Jun, Taewhan Kim:
An efficient inverse multiplier/divider architecture for cryptography systems. ISCAS (5) 2003: 149-152 - 2002
- [c5]Junhyung Um, Taewhan Kim:
Layout-aware synthesis of arithmetic circuits. DAC 2002: 207-212 - [c4]Junhyung Um, Jae-Hoon Kim, Taewhan Kim:
Layout-driven resource sharing in high-level synthesis. ICCAD 2002: 614-618 - 2001
- [j2]Junhyung Um, Taewhan Kim:
An Optimal Allocation of Carry-Save-Adders in Arithmetic Circuits. IEEE Trans. Computers 50(3): 215-233 (2001) - 2000
- [j1]Taewhan Kim, Junhyung Um:
A practical approach to the synthesis of arithmetic circuits usingcarry-save-adders. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(5): 615-624 (2000) - [c3]Taewhan Kim, Junhyung Um:
A timing-driven synthesis of arithmetic circuits using carry-save-adders (short paper). ASP-DAC 2000: 313-316 - [c2]Junhyung Um, Taewhan Kim, C. L. Liu:
A fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis. DAC 2000: 98-103
1990 – 1999
- 1999
- [c1]Junhyung Um, Taewhan Kim, C. L. Liu:
Optimal allocation of carry-save-adders in arithmetic optimization. ICCAD 1999: 410-413
Coauthor Index
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