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2020 – today
- 2024
[c11]Jasmina Vasiljevic, Davor Capalija:
Blackhole & TT-Metalium: The Standalone AI Computer and its Programming Model. HCS 2024: 1-30- 2021
- [j2]Jasmina Vasiljevic
, Ljubisa Bajic, Davor Capalija, Stanislav Sokorac, Dragoljub Ignjatovic, Lejla Bajic, Milos Trajkovic, Ivan Hamer, Ivan Matosevic, Aleksandar Cejkov, Utku Aydonat, Tony Zhou, Syed Zohaib Gilani, Armond Paiva, Joseph Chu, Djordje Maksimovic, Stephen Alexander Chin, Zahi Moudallal, Akhmed Rakhmati, Sean Nijjar, Almeet Bhullar, Boris Drazic, Charles Lee, James Sun, Kei-Ming Kwong, James Connolly, Miles Dooley, Hassan Farooq, Joy Yu Ting Chen, Matthew Walker, Keivan Dabiri, Kyle Mabee, Rakesh Shaji Lal, Namal Rajatheva, Renjith Retnamma, Shripad Karodi, Daniel Rosen, Emilio Munoz, Andrew Lewycky, Aleksandar Knezevic, Raymond Kim, Allan Rui, Alexander Drouillard, David Thompson:
Compute Substrate for Software 2.0. IEEE Micro 41(2): 50-55 (2021)
2010 – 2019
- 2018
- [c10]Eriko Nurvitadhi, Jeffrey J. Cook, Asit K. Mishra, Debbie Marr, Kevin Nealis, Philip Colangelo, Andrew C. Ling, Davor Capalija, Utku Aydonat, Sergey Y. Shumarayev, Aravind Dasu:
In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC(Abstract Only). FPGA 2018: 287 - [c9]Eriko Nurvitadhi, Jeffrey J. Cook, Asit K. Mishra, Debbie Marr, Kevin Nealis, Philip Colangelo, Andrew C. Ling, Davor Capalija, Utku Aydonat, Aravind Dasu, Sergey Y. Shumarayev:
In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC. FPL 2018: 106-110 - [c8]Gordon R. Chiu, Andrew C. Ling, Davor Capalija, Andrew Bitar, Mohamed S. Abdelfattah:
Flexibility: FPGAs and CAD in Deep Learning Acceleration. ISPD 2018: 34-41 - 2017
- [c7]Utku Aydonat, Shane O'Connell, Davor Capalija, Andrew C. Ling, Gordon R. Chiu:
An OpenCL™ Deep Learning Accelerator on Arria 10. FPGA 2017: 55-64 - [c6]Jack Yinger, Eriko Nurvitadhi, Davor Capalija, Andrew C. Ling, Debbie Marr, Krishnan Srivatsan, Duncan J. M. Moss, Suchit Subhaschandra:
Customizable FPGA OpenCL matrix multiply design template for deep neural networks. FPT 2017: 259-262 - [c5]Andrew C. Ling, Utku Aydonat, Shane O'Connell, Davor Capalija, Gordon R. Chiu:
Creating High Performance Applications with Intel's FPGA OpenCL™ SDK. IWOCL 2017: 11:1 - [i1]Utku Aydonat, Shane O'Connell, Davor Capalija, Andrew C. Ling, Gordon R. Chiu:
An OpenCL(TM) Deep Learning Accelerator on Arria 10. CoRR abs/1701.03534 (2017) - 2014
- [c4]Davor Capalija, Tarek S. Abdelrahman:
Tile-based bottom-up compilation of custom mesh-of-functional-units FPGA overlays. FPL 2014: 1-8 - 2013
- [j1]Davor Capalija, Tarek S. Abdelrahman:
Microarchitecture of a Coarse-Grain Out-of-Order Superscalar Processor. IEEE Trans. Parallel Distributed Syst. 24(2): 392-405 (2013) - [c3]Davor Capalija, Tarek S. Abdelrahman:
A high-performance overlay architecture for pipelined execution of data flow graphs. FPL 2013: 1-8 - 2011
- [c2]Davor Capalija, Tarek S. Abdelrahman:
Towards Synthesis-Free JIT Compilation to Commodity FPGAs. FCCM 2011: 202-205
2000 – 2009
- 2006
- [c1]Blair Fort, Davor Capalija, Zvonko G. Vranesic, Stephen Dean Brown:
A Multithreaded Soft Processor for SoPC Area Reduction. FCCM 2006: 131-142
Coauthor Index
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