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ORCIDCASES 2015: Amsterdam, The Netherlands
- Ravi Iyer, Siddharth Garg:
2015 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES 2015, Amsterdam, The Netherlands, October 4-9, 2015. IEEE 2015, ISBN 978-1-4673-8320-2 - Xuejing He, Robert P. Dick, Russ Joseph:
Embedded system and application aware design of deregulated energy delivery systems. 1-10 - Matthew Schuchhardt, Susmit Jha, Raid Ayoub, Michael Kishinevsky, Gokhan Memik:
Optimizing mobile display brightness by leveraging human visual perception. 11-20 - Darshana Jayasinghe, Aleksandar Ignjatovic, Jude Angelo Ambrose, Roshan G. Ragel, Sri Parameswaran
:
QuadSeal: Quadruple algorithmic symmetrizing countermeasure against power based side-channel attacks. 21-30 - Hadi Esmaeilzadeh:
Approximate acceleration: A path through the era of dark silicon and big data. 31-32 - Ashutosh Ingole, Biswaroop Maiti, John Augustine, Krishna V. Palem:
Does customizing inexactness help over simplistic precision (bit-width) reduction? A case study. 33-34 - Alexei Colin, Alanson P. Sample, Brandon Lucia:
Energy-interference-free system and toolchain support for energy-harvesting devices. 35-36 - Sasa Misailovic:
Accuracy-aware optimization of approximate programs. 37-38 - Liangzhen Lai, Vikas Chandra, Puneet Gupta:
Evaluating and exploiting impacts of dynamic power management schemes on system reliability. 39-48 - Thiago Santini, Paolo Rech, Luigi Carro, Flávio Rech Wagner:
Exploiting cache conflicts to reduce radiation sensitivity of operating systems on embedded systems. 49-58 - Russ Dill, Aviral Shrivastava, Hyunok Oh:
Optimization of multi-channel BCH error decoding for common cases. 59-68 - Pooja Roy, Jianxing Wang, Weng-Fai Wong:
PAC: Program Analysis for Approximation-aware Compilation. 69-78 - Felipe Sampaio, Muhammad Shafique, Bruno Zatt, Sergio Bampi, Jörg Henkel:
Approximation-aware Multi-Level Cells STT-RAM cache architecture. 79-88 - Arnab Raha, Hrishikesh Jayakumar, Soubhagya Sutar, Vijay Raghunathan:
Quality-aware data allocation in approximate DRAM? 89-98 - Yi-Ping You, Szu-Chieh Chen:
Vector-aware register allocation for GPU shader processors. 99-108 - Eriko Nurvitadhi, Asit K. Mishra, Debbie Marr:
A sparse matrix vector multiply accelerator for support vector machine. 109-116 - Marco A. Z. Alves, Paulo C. Santos, Francis B. Moreira, Matthias Diener, Luigi Carro:
Saving memory movements through vector processing in the DRAM. 117-126 - Weichen Liu, Zonghua Gu, Yaoyao Ye:
Efficient SAT-based application mapping and scheduling on multiprocessor systems for throughput maximization. 127-136 - Ahmed Nassar, Fadi J. Kurdahi, Wael M. Elsharkasy:
NUVA: Architectural support for runtime verification of parametric specifications over multicores. 137-146 - Karthi Duraisamy, Hao Lu, Partha Pratim Pande, Ananth Kalyanaraman:
High performance and energy efficient wireless NoC-enabled multicore architectures for graph analytics. 147-156 - Maria A. Serrano, Alessandra Melani, Roberto Vargas, Andrea Marongiu, Marko Bertogna, Eduardo Quiñones:
Timing characterization of OpenMP4 tasking model. 157-166 - B. Davis, Ryan Baird, Peter Gavin, Magnus Själander, Ian Finlayson, F. Rasapour, G. Cook, Gang-Ryung Uh, David B. Whalley, Gary S. Tyson:
Scheduling instruction effects for a statically pipelined processor. 167-176 - Ehsan Atoofian:
Reducing shift penalty in Domain Wall Memory through register locality. 177-186 - Veena Misra, Benton H. Calhoun, Shekhar Bhansali, John C. Lach, Suman Datta, Mehmet Ozturk, Alper Bozkurt, Ömer Oralkan, Jason Strohmaier:
Self-powered wearable sensor platforms for wellness. 187 - Kevin M. Irick, Peter A. Zientara, Jack Sampson, Vijaykrishnan Narayanan:
Cognitive cameras: Assistive vision systems. 188 - Yongpan Liu, Hehe Li, Xueqing Li, Chun Jason Xue, Yuan Xie, Huazhong Yang:
Self-powered wearable sensor node: Challenges and opportunities. 189
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