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ORCIDJude Angelo Ambrose
Person information
- affiliation: University of New South Wales, Sydney, Australia
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2020 – today
- 2021
[j7]Darshana Jayasinghe, Aleksandar Ignjatovic, Roshan G. Ragel, Jude Angelo Ambrose, Sri Parameswaran:
QuadSeal: Quadruple Balancing to Mitigate Power Analysis Attacks with Variability Effects and Electromagnetic Fault Injection Attacks. ACM Trans. Design Autom. Electr. Syst. 26(5): 33:1-33:36 (2021)
2010 – 2019
- 2017
- [j6]Tuo Li, Muhammad Shafique
, Jude Angelo Ambrose, Jörg Henkel, Sri Parameswaran:
Fine-Grained Checkpoint Recovery for Application-Specific Instruction-Set Processors. IEEE Trans. Computers 66(4): 647-660 (2017) - 2016
- [j5]Tuo Li, Jude Angelo Ambrose, Roshan G. Ragel, Sri Parameswaran:
Processor Design for Soft Errors: Challenges and State of the Art. ACM Comput. Surv. 49(3): 57:1-57:44 (2016) - [c35]Tuo Li, Jude Angelo Ambrose, Sri Parameswaran:
RECORD: Reducing register traffic for checkpointing in embedded processors. DATE 2016: 582-587 - 2015
- [c34]Xi Zhang, Haris Javaid, Muhammad Shafique, Jude Angelo Ambrose, Jörg Henkel, Sri Parameswaran:
ADAPT: An adaptive manycore methodology for software pipelined applications. ASP-DAC 2015: 701-706 - [c33]Darshana Jayasinghe, Aleksandar Ignjatovic, Jude Angelo Ambrose, Roshan G. Ragel, Sri Parameswaran:
QuadSeal: Quadruple algorithmic symmetrizing countermeasure against power based side-channel attacks. CASES 2015: 21-30 - [c32]Liang Tang, Jude Angelo Ambrose, Akash Kumar, Sri Parameswaran:
Dynamic reconfigurable puncturing for secure wireless communication. DATE 2015: 888-891 - [c31]Jude Angelo Ambrose, Yusuke Yachide, Kapil Batra, Jorgen Peddersen, Sri Parameswaran:
Sequential C-code to distributed pipelined heterogeneous MPSoC synthesis for streaming applications. ICCD 2015: 216-223 - [c30]Jude Angelo Ambrose, Nick Higgins, Mrinal Chakravarthy, Shivam Gargg, Tuo Li, Daniel Murphy, Aleksandar Ignjatovic, Sri Parameswaran:
ARCHER: Communication-based predictive architecture selection for application specific multiprocessor Systems-on-Chip. ISCAS 2015: 413-416 - [c29]Jude Angelo Ambrose, Roshan G. Ragel, Darshana Jayasinghe, Tuo Li, Sri Parameswaran:
Side channel attacks in embedded systems: A tale of hostilities and deterrence. ISQED 2015: 452-459 - [c28]Jude Angelo Ambrose, Tuo Li, Daniel Murphy, Shivam Gargg, Nick Higgins, Sri Parameswaran:
ARGUS: A Framework for Rapid Design and Prototype of Heterogeneous Multicore Systems in FPGA. VLSID 2015: 29-34 - [i2]Roshan G. Ragel, Jude Angelo Ambrose, Sri Parameswaran:
SecureD: A Secure Dual Core Embedded Processor. CoRR abs/1511.01946 (2015) - 2014
- [c27]Jude Angelo Ambrose, Jorgen Peddersen, Sri Parameswaran, Alvin Labios, Yusuke Yachide:
SDG2KPN: System Dependency Graph to function-level KPN generation of legacy code for MPSoCs. ASP-DAC 2014: 267-273 - [c26]Darshana Jayasinghe, Roshan G. Ragel, Jude Angelo Ambrose, Aleksandar Ignjatovic, Sri Parameswaran:
Advanced modes in AES: Are they safe from power analysis based side channel attacks? ICCD 2014: 173-180 - [c25]Héctor Pettenghi, Jude Angelo Ambrose, Ricardo Chaves, Leonel Sousa:
Method for designing multi-channel RNS architectures to prevent power analysis SCA. ISCAS 2014: 2233-2236 - [c24]Vinitha Arakkonam Palaniveloo, Jude Angelo Ambrose, Arcot Sowmya:
Improving GA-Based NoC Mapping Algorithms Using a Formal Model. ISVLSI 2014: 344-349 - [c23]Liang Tang, Jude Angelo Ambrose, Sri Parameswaran, Sha Zhu:
Reconfigurable Convolutional Codec for Physical Layer Communication Security Application. MILCOM 2014: 82-87 - [i1]Roshan G. Ragel, Swarnalatha Radhakrishnan, Jude Angelo Ambrose:
Instruction-set Selection for Multi-application based ASIP Design: An Instruction-level Study. CoRR abs/1403.7291 (2014) - 2013
- [j4]Jude Angelo Ambrose, Héctor Pettenghi, Darshana Jayasinghe, Leonel Sousa:
Randomised multi-modulo residue number system architecture for double-and-add to prevent power analysis side channel attacks. IET Circuits Devices Syst. 7(5): 283-293 (2013) - [c22]Jude Angelo Ambrose, Héctor Pettenghi, Leonel Sousa:
DARNS: A randomized multi-modulo RNS architecture for double-and-add in ECC to prevent power analysis side channel attacks. ASP-DAC 2013: 620-625 - [c21]Tuo Li, Muhammad Shafique, Jude Angelo Ambrose, Semeen Rehman, Jörg Henkel, Sri Parameswaran:
RASTER: runtime adaptive spatial/temporal error resiliency for embedded processors. DAC 2013: 62:1-62:7 - [c20]Liang Tang, Jude Angelo Ambrose, Sri Parameswaran:
Reconfigurable pipelined coprocessor for multi-mode communication transmission. DAC 2013: 134:1-134:8 - [c19]Tuo Li, Muhammad Shafique, Semeen Rehman, Swarnalatha Radhakrishnan, Roshan G. Ragel, Jude Angelo Ambrose, Jörg Henkel, Sri Parameswaran:
CSER: HW/SW configurable soft-error resiliency for application specific instruction-set processors. DATE 2013: 707-712 - [c18]Lawrance Zhang, Jude Angelo Ambrose, Jorgen Peddersen, Sri Parameswaran, Roshan G. Ragel, Swarnalatha Radhakrishnan, Kewal K. Saluja:
DRMA: dynamically reconfigurable MPSoC architecture. ACM Great Lakes Symposium on VLSI 2013: 239-244 - [c17]Tuo Li, Muhammad Shafique, Semeen Rehman, Jude Angelo Ambrose, Jörg Henkel, Sri Parameswaran:
DHASER: dynamic heterogeneous adaptation for soft-error resiliency in ASIP-based multi-core systems. ICCAD 2013: 646-653 - [c16]Liang Tang, Jude Angelo Ambrose, Sri Parameswaran:
Variable increment step based reconfigurable interleaver for multimode communication application. ISCAS 2013: 73-76 - [c15]Jude Angelo Ambrose, Isuru Nawinne, Sri Parameswaran:
Latency-constrained binding of data flow graphs to energy conscious GALS-based MPSoCs. ISCAS 2013: 1212-1215 - [c14]Ankita Arora, Jude Angelo Ambrose, Jorgen Peddersen, Sri Parameswaran:
A double-width algorithmic balancing to prevent power analysis Side Channel Attacks in AES. ISVLSI 2013: 76-83 - [c13]Liang Tang, Jude Angelo Ambrose, Sri Parameswaran:
MAPro: A Tiny Processor for Reconfigurable Baseband Modulation Mapping. VLSI Design 2013: 1-6 - [c12]Roshan G. Ragel, Swarnalatha Radhakrishnan, Jude Angelo Ambrose, Sri Parameswaran:
A Study on Instruction-set Selection Using Multi-application Based Application Specific Instruction-set Processors. VLSI Design 2013: 7-12 - 2012
- [j3]Jude Angelo Ambrose, Roshan G. Ragel, Sri Parameswaran:
Randomized Instruction Injection to Counter Power Analysis Attacks. ACM Trans. Embed. Comput. Syst. 11(3): 69:1-69:28 (2012) - [c11]Héctor Pettenghi, Leonel Sousa, Jude Angelo Ambrose:
Efficient implementation of multi-moduli architectures for Binary-to-RNS conversion. ASP-DAC 2012: 819-824 - [c10]Mohammad Shihabul Haque, Roshan G. Ragel, Jude Angelo Ambrose, Swarnalatha Radhakrishnan, Sri Parameswaran:
DIMSim: a rapid two-level cache simulation approach for deadline-based MPSoCs. CODES+ISSS 2012: 151-160 - [c9]Radu Andrei Stefan, Anca Mariana Molnos, Jude Angelo Ambrose, Kees Goossens:
A TDM NoC supporting QoS, multicast, and fast connection set-up. DATE 2012: 1283-1288 - [c8]Tuo Li, Jude Angelo Ambrose, Sri Parameswaran:
Fine-grained hardware/software methodology for process migration in MPSoCs. ICCAD 2012: 508-515 - [c7]Jude Angelo Ambrose, Aleksandar Ignjatovic, Sri Parameswaran:
CoRaS: A multiprocessor key corruption and random round swapping for power analysis side channel attacks: A DES case study. ISCAS 2012: 253-256 - 2011
- [j2]Jude Angelo Ambrose, Roshan G. Ragel, Sri Parameswaran, Aleksandar Ignjatovic:
Multiprocessor information concealment architecture to prevent power analysis-based side channel attacks. IET Comput. Digit. Tech. 5(1): 1-15 (2011) - [j1]Andreas Hansson, Marcus Ekerhult, Anca Mariana Molnos, Aleksandar Milutinovic, Andrew Nelson, Jude Angelo Ambrose, Kees Goossens:
Design and implementation of an operating system for composable processor sharing. Microprocess. Microsystems 35(2): 246-260 (2011) - [c6]Jude Angelo Ambrose, Anca Mariana Molnos, Andrew Nelson, Sorin Cotofana, Kees Goossens, Ben H. H. Juurlink:
Composable local memory organisation for streaming applications on embedded MPSoCs. Conf. Computing Frontiers 2011: 23 - [p1]Benny Akesson, Anca Mariana Molnos, Andreas Hansson, Jude Angelo Ambrose, Kees Goossens:
Composability and Predictability for Independent Application Development, Verification, and Execution. Multiprocessor System-on-Chip 2011: 25-56 - 2010
- [c5]Roshan G. Ragel, Jude Angelo Ambrose, Jorgen Peddersen, Sri Parameswaran:
RACE: A Rapid, ArChitectural Simulation and Synthesis Framework for Embedded Processors. DIPES/BICC 2010: 137-144
2000 – 2009
- 2009
- [b2]Jude Angelo Ambrose:
Power analysis side channel attacks: the processor design-level context. University of New South Wales, Sydney, Australia, 2009 - [b1]Jude Angelo Ambrose:
Power analysis side channel attacks: the processor design-level context. University of New South Wales, Sydney, Australia, 2009 - 2008
- [c4]Jude Angelo Ambrose, Sri Parameswaran, Aleksandar Ignjatovic:
MUTE-AES: a multiprocessor architecture to prevent power analysis based side channel attack of the AES algorithm. ICCAD 2008: 678-684 - [c3]Jude Angelo Ambrose, Naeill Aldon, Aleksandar Ignjatovic, Sri Parameswaran:
Anatomy of Differential Power Analysis for AES. SYNASC 2008: 459-466 - 2007
- [c2]Jude Angelo Ambrose, Roshan G. Ragel, Sri Parameswaran:
A smart random code injection to mask power analysis based side channel attacks. CODES+ISSS 2007: 51-56 - [c1]Jude Angelo Ambrose, Roshan G. Ragel, Sri Parameswaran:
RIJID: Random Code Injection to Mask Power Analysis based Side Channel Attacks. DAC 2007: 489-492
Coauthor Index
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