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ORCIDSwarnalatha Radhakrishnan
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2010 – 2019
- 2015
[j2]Isuru Nawinne, Haris Javaid, Roshan G. Ragel, Swarnalatha Radhakrishnan, Sri Parameswaran
:
Exploring Multilevel Cache Hierarchies in Application Specific MPSoCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(12): 1991-2003 (2015)- 2014
- [i3]B. A. N. M. Bambarasinghe, H. M. S. Huruggamuwa, Roshan G. Ragel, Swarnalatha Radhakrishnan:
Axis2UNO: Web Services Enabled Openoffice.org. CoRR abs/1402.0670 (2014) - [i2]Rajitha Navarathna, Swarnalatha Radhakrishnan, Roshan G. Ragel:
Loop Unrolling in Multi-pipeline ASIP Design. CoRR abs/1402.0671 (2014) - [i1]Roshan G. Ragel, Swarnalatha Radhakrishnan, Jude Angelo Ambrose:
Instruction-set Selection for Multi-application based ASIP Design: An Instruction-level Study. CoRR abs/1403.7291 (2014) - 2013
- [c7]Tuo Li, Muhammad Shafique, Semeen Rehman, Swarnalatha Radhakrishnan, Roshan G. Ragel, Jude Angelo Ambrose, Jörg Henkel, Sri Parameswaran:
CSER: HW/SW configurable soft-error resiliency for application specific instruction-set processors. DATE 2013: 707-712 - [c6]Lawrance Zhang, Jude Angelo Ambrose, Jorgen Peddersen, Sri Parameswaran, Roshan G. Ragel, Swarnalatha Radhakrishnan, Kewal K. Saluja:
DRMA: dynamically reconfigurable MPSoC architecture. ACM Great Lakes Symposium on VLSI 2013: 239-244 - [c5]Roshan G. Ragel, Swarnalatha Radhakrishnan, Jude Angelo Ambrose, Sri Parameswaran:
A Study on Instruction-set Selection Using Multi-application Based Application Specific Instruction-set Processors. VLSI Design 2013: 7-12 - 2012
- [c4]Mohammad Shihabul Haque, Roshan G. Ragel, Jude Angelo Ambrose, Swarnalatha Radhakrishnan, Sri Parameswaran:
DIMSim: a rapid two-level cache simulation approach for deadline-based MPSoCs. CODES+ISSS 2012: 151-160
2000 – 2009
- 2009
- [j1]Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran, Aleksandar Ignjatovic:
HMP-ASIPs: heterogeneous multi-pipeline application-specific instruction-set processors. IET Comput. Digit. Tech. 3(1): 94-108 (2009) - 2006
- [b1]Swarnalatha Radhakrishnan:
Heterogeneous multi-pipeline application specific instruction-set processor design and implementation. University of New South Wales, Sydney, Australia, 2006 - [c3]Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran, Aleksandar Ignjatovic:
Application specific forwarding network and instruction encoding for multi-pipe ASIPs. CODES+ISSS 2006: 241-246 - [c2]Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran:
Customization of application specific heterogeneous multi-pipeline processors. DATE 2006: 746-751 - 2004
- [c1]Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran:
Dual-pipeline heterogeneous ASIP design. CODES+ISSS 2004: 12-17
Coauthor Index
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