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ORCIDJean Jyh-Jiun Shann
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2010 – 2019
- 2017
[c18]Han-Ping Lo, Jean Jyh-Jiun Shann:
Translating OpenACC program for HAS environment. CITS 2017: 30-34- 2016
- [c17]Hao-Wei Peng, Jean Jyh-Jiun Shann:
Translating OpenACC to LLVM IR with SPIR kernels. ICIS 2016: 1-6 - 2015
- [j14]I-Wei Wu, Jean Jyh-Jiun Shann, Chung-Ping Chung:
Reconfigurable Custom Functional Unit Generation and Exploitation for Multiple-Issue Processors. J. Inf. Sci. Eng. 31(4): 1431-1453 (2015) - [c16]I-Chun Liu, I-Wei Wu, Jean Jyh-Jiun Shann:
Instruction Emulation and OS Supports of a Hybrid Binary Translator for x86 Instruction Set Architecture. UIC/ATC/ScalCom 2015: 1070-1077 - 2014
- [j13]I-Wei Wu, Jean Jyh-Jiun Shann, Wei-Chung Hsu
, Chung-Ping Chung:
Extended Instruction Exploration for Multiple-Issue Architectures. ACM Trans. Embed. Comput. Syst. 13(4): 92:1-92:28 (2014) - 2013
- [c15]Yu-Hsin Tsai, I-Wei Wu, I-Chun Liu, Jean Jyh-Jiun Shann:
Improving performance of JNA by using LLVM JIT compiler. ICIS 2013: 483-488 - 2012
- [j12]Kuen-Cheng Chiang, Ming-Feng Wu, Jean Jyh-Jiun Shann:
Modification and implementation of an edge-based fast intra prediction mode decision algorithm for H.264/AVC high resolution real-time systems. J. Vis. Commun. Image Represent. 23(2): 245-253 (2012) - [c14]Jhin-Bin Jiang, Kuen-Cheng Chiang, Jean Jyh-Jiun Shann:
A predicate-aware modulo scheduling for improving resource efficiency of coarse grained reconfigurable architectures. SIES 2012: 311-314 - 2011
- [j11]I-Wei Wu, Chung-Ping Chung, Jean Jyh-Jiun Shann:
Area-Efficient Instruction Set Extension Exploration with Hardware Design Space Exploration. J. Inf. Sci. Eng. 27(5): 1641-1657 (2011) - 2010
- [c13]Hui-Shan Wang, I-Wei Wu, Jean Jyh-Jiun Shann, Chung-Ping Chung:
Reconfigurable custom functional unit generation and exploitation in multiple-issue processors. SASP 2010: 115-118
2000 – 2009
- 2009
- [c12]Jyh-Shian Wang, I-Wei Wu, Yu-Sheng Chen, Jean Jyh-Jiun Shann, Wei-Chung Hsu:
Reducing Code Size by Graph Coloring Register Allocation and Assignment Algorithm for Mixed-Width ISA Processor. CSE (2) 2009: 174-181 - [c11]Hsiu-ching Hsieh, Chih-Chieh Hsiao, Hui-Chin Yang, Chung-Ping Chung, Jean Jyh-Jiun Shann:
Methods for Precise False-Overlap Detection in Tile-Based Rendering. CSE (2) 2009: 414-419 - 2008
- [c10]Po-Chun Chang, I-Wei Wu, Jean Jyh-Jiun Shann, Chung-Ping Chung:
ETAHM: an energy-aware task allocation algorithm for heterogeneous multiprocessor. DAC 2008: 776-779 - [c9]I-Wei Wu, Zhiyuan Chen, Jean Jyh-Jiun Shann, Chung-Ping Chung:
Instruction Set Extension Exploration in Multiple-Issue Architecture. DATE 2008: 764-769 - 2007
- [c8]I-Wei Wu, Shih-Chia Huang, Chung-Ping Chung, Jean Jyh-Jiun Shann:
Instruction Set Extension Generation with Considering Physical Constraints. HiPEAC 2007: 291-305 - 2006
- [j10]Cher-Sheng Cheng, Jean Jyh-Jiun Shann, Chung-Ping Chung:
Unique-order interpolative coding for fast querying and space-efficient indexing in information retrieval systems. Inf. Process. Manag. 42(2): 407-428 (2006) - [j9]Cher-Sheng Cheng, Chung-Ping Chung, Jean Jyh-Jiun Shann:
Fast query evaluation through document identifier assignment for inverted file-based information retrieval systems. Inf. Process. Manag. 42(3): 729-750 (2006) - [c7]Kuen-Cheng Chiang, Zhi-Wei Chen, Jean Jyh-Jiun Shann:
Design and implementation of a reconfigurable hardware for secure embedded systems. AsiaCCS 2006: 364 - 2005
- [c6]Wei-Hao Chiao, Tsung-Hsi Weng, Jean Jyh-Jiun Shann, Chung-Ping Chung, Jimmy Lu:
Low-Power Data Address Bus Encoding Method. CDES 2005: 204-210 - [c5]Yau-Chong Hu, Wei-Hau Chiao, Jean Jyh-Jiun Shann, Chung-Ping Chung, Wen-Feng Chen:
Low-Power Branch Prediction. CDES 2005: 211-217 - 2004
- [j8]Kelvin Lin, Jean Jyh-Jiun Shann, Chung-Ping Chung:
Code compression by register operand dependency. J. Syst. Softw. 72(3): 295-304 (2004) - [j7]Lee-Ren Ton, Lung-Chung Chang, Jean Jyh-Jiun Shann, Chung-Ping Chung:
A software/hardware cooperated stack operations folding model for Java processors. J. Syst. Softw. 72(3): 377-387 (2004) - [c4]Cher-Sheng Cheng, Jean Jyh-Jiun Shann, Chung-Ping Chung:
A Unique-Order Interpolative Code for Fast Querying and Space-Efficient Indexing in Information Retrieval Systems. ITCC (2) 2004: 229-235 - 2003
- [j6]Wann-Yun Shieh, Tien-Fu Chen, Jean Jyh-Jiun Shann, Chung-Ping Chung:
Inverted file compression through document identifier reassignment. Inf. Process. Manag. 39(1): 117-131 (2003) - [j5]Wann-Yun Shieh, Jean Jyh-Jiun Shann, Chung-Ping Chung:
An Inverted File Cache for Fast Information Retrieval. J. Inf. Sci. Eng. 19(4): 681-695 (2003) - [j4]Kelvin Lin, Chung-Ping Chung, Jean Jyh-Jiun Shann:
Compressing MIPS code by multiple operand dependencies. ACM Trans. Embed. Comput. Syst. 2(4): 482-508 (2003) - 2002
- [j3]Lee-Ren Ton, Lung-Chung Chang, Jean Jyh-Jiun Shann, Chung-Ping Chung:
Design of an optimal folding mechanism for Java processors. Microprocess. Microsystems 26(8): 341-352 (2002) - [c3]Kelvin Lin, Jean Jyh-Jiun Shann, Chung-Ping Chung:
Code Compression by Register Operand Dependency. Interaction between Compilers and Computer Architectures 2002: 91-101 - 2001
- [j2]R.-Ming Shiu, Hui-Yue Hwang, Jean Jyh-Jiun Shann:
Aggressive Schduling for Memory Accesses of CISC Superscalar Microprocessors. J. Inf. Sci. Eng. 17(5): 787-803 (2001)
1990 – 1999
- 1998
- [c2]S.-K. Cheng, R.-Ming Shiu, Jean Jyh-Jiun Shann:
Decoding Unit with High Issue Rate for X86 Superscalar Microprocessors. ICPADS 1998: 488-495 - [c1]Hui-Yue Hwang, R.-Ming Shiu, Jean Jyh-Jiun Shann:
An X86 Load/Store Unit with Aggressive Scheduling of Load/Store Operations. ICPADS 1998: 496-503 - 1994
- [j1]Hsin-Chia Fu, Jean Jyh-Jiun Shann:
A Fuzzy Neural Network for Knowledge Learning. Int. J. Neural Syst. 5(1): 13-22 (1994)
Coauthor Index
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