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2020 – today
- 2025
[j58]Michihiro Koibuchi:
Foreword. IEICE Trans. Inf. Syst. 108(1): 1 (2025)- [j57]Kenji Mizutani, Yutaka Urino, Takanori Shimizu, Hiroshi Yamaguchi, Shigeru Nakamura, Tatsuya Usuki, Kiyo Ishii, Ryosuke Matsumoto, Takashi Inoue, Shu Namiki, Michihiro Koibuchi:
In-network stable radix sorter using many FPGAs with high-bandwidth photonics [Invited]. J. Opt. Commun. Netw. 17(1): 34 (2025) - 2024
- [c129]Kien Trung Pham, Truong Thao Nguyen, Michihiro Koibuchi:
A Bandwidth-Optimal All-to-All Communication in Two-Dimensional Fully Connected Network. CCGrid 2024: 1-7 - [c128]Kenji Mizutani, Yutaka Urino, Takanori Shimizu, Hiroshi Yamaguchi, Shigeru Nakamura, Tatsuya Usuki, Kiyo Ishii, Ryosuke Matsumoto, Takashi Inoue, Shu Namiki, Michihiro Koibuchi:
Performance of Radix Sort using All-to-all Optical Interconnection Network in an Eight-FPGA Cluster. OFC 2024: 1-3 - 2023
- [j56]Toshiki Ishimaru, Takatomo Mihana
, Michihiro Koibuchi, Tetsuya Kawanishi, Makoto Naruse:
Experimental Demonstration of Approximate Communication Based on Radio-Over- Fiber Systems. IEEE Access 11: 65590-65598 (2023) - [j55]Ryota Yasudo, Koji Nakano, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano:
Designing low-diameter interconnection networks with multi-ported host-switch graphs. Concurr. Comput. Pract. Exp. 35(11) (2023) - [j54]Naoya Niwa, Yoshiya Shikama, Hideharu Amano, Michihiro Koibuchi:
A Compression Router for Low-Latency Network-on-Chip. IEICE Trans. Inf. Syst. 106(2): 170-180 (2023) - [j53]Truong Thao Nguyen, Kien Trung Pham, Hiroshi Yamaguchi, Yutaka Urino, Michihiro Koibuchi:
Effective switchless inter-FPGA memory networks. J. Parallel Distributed Comput. 179: 104713 (2023) - [c127]Naoki Shibahara, Michihiro Koibuchi, Hiroki Matsutani:
Performance Improvement of Federated Learning Server using Smart NIC. CANDARW 2023: 165-171 - [c126]Shoichi Hirasawa, Michihiro Koibuchi:
An Auto-Tuning Method for High-Bandwidth Low-Latency Approximate Interconnection Networks. PDP 2023: 9-16 - [i2]Naoki Shibahara, Michihiro Koibuchi, Hiroki Matsutani:
A Case for Offloading Federated Learning Server on Smart NIC. CoRR abs/2307.06561 (2023) - 2022
- [j52]Naoya Niwa, Hideharu Amano, Michihiro Koibuchi:
Boosting the Performance of Interconnection Networks by Selective Data Compression. IEICE Trans. Inf. Syst. 105-D(12): 2057-2065 (2022) - [j51]Kenji Mizutani, Hiroshi Yamaguchi, Yutaka Urino, Michihiro Koibuchi:
Accelerating parallel data processing using optically tightly coupled FPGAs. JOCN 14(2): A166-A179 (2022) - [j50]Yoshiya Shikama, Ryuta Kawano, Hiroki Matsutani, Hideharu Amano, Yusuke Nagasaka, Naoto Fukumoto, Michihiro Koibuchi:
A traffic-aware memory-cube network using bypassing. Microprocess. Microsystems 90: 104471 (2022) - [c125]Yutaka Urino, Takanori Shimizu, Hiroshi Yamaguchi, Kenji Mizutani, Shigeru Nakamura, Tatsuya Usuki, Michihiro Koibuchi:
A Scalable Distributed Radix Sorter for FPGA Clusters using High-Bandwidth Memory Networks. FCCM 2022: 1 - [c124]Ryuta Kawano, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Dynamic Routing Reconfiguration for Low-Latency and Deadlock-Free Interconnection Networks. CANDAR 2022: 117-123 - [c123]Jacir Luiz Bordim, Michihiro Koibuchi, Satoshi Fujita, Koji Nakano:
Message from the Organizers: CANDAR 2022. CANDAR 2022: viii - [c122]Kien Trung Pham, Truong Thao Nguyen, Hiroshi Yamaguchi, Yutaka Urino, Michihiro Koibuchi:
Scalable Low-Latency Inter-FPGA Networks. IPDPS 2022: 234-245 - [c121]Yoshiya Shikama, Michihiro Koibuchi, Hideharu Amano:
A Hardware Trojan Exploiting Coherence Protocol on NoCs. PDCAT 2022: 301-313 - [c120]Ke Cui, Michihiro Koibuchi:
A High-Radix Circulant Network Topology for Efficient Collective Communication. PDCAT 2022: 401-412 - 2021
- [j49]Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Yao Hu, Michihiro Koibuchi, Hideharu Amano:
Improving the Performance of Circuit-Switched Interconnection Network for a Multi-FPGA System. IEICE Trans. Inf. Syst. 104-D(12): 2029-2039 (2021) - [j48]Tomoya Itsubo, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani:
An FPGA-Based Optimizer Design for Distributed Deep Learning with Multiple GPUs. IEICE Trans. Inf. Syst. 104-D(12): 2057-2067 (2021) - [j47]Kenji Mizutani, Hiroshi Yamaguchi, Yutaka Urino, Michihiro Koibuchi:
OPTWEB: A Lightweight Fully Connected Inter-FPGA Network for Efficient Collectives. IEEE Trans. Computers 70(6): 849-862 (2021) - [c119]Ryuta Kawano, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
GPU Parallelization of All-Pairs-Shortest-Path Algorithm in Low-Degree Unweighted Regular Graph. ACIT 2021: 51-55 - [c118]Shoichi Hirasawa, Hayato Yamaki, Michihiro Koibuchi:
Packet Forwarding Cache of Commodity Switches for Parallel Computers. CLUSTER 2021: 366-376 - [c117]Naoya Niwa, Hideharu Amano, Michihiro Koibuchi:
Low-Latency High-Bandwidth Interconnection Networks by Selective Packet Compression. CANDAR 2021: 56-64 - [c116]Yao Hu, Michihiro Koibuchi:
The Case for Disjoint Job Mapping on High-Radix Networked Parallel Computers. ICA3PP (2) 2021: 123-143 - [c115]Yao Hu, Michihiro Koibuchi:
Accelerating MPI Communication Using Floating-point Compression on Lossy Interconnection Networks. LCN 2021: 355-358 - [c114]Kenji Mizutani, Hiroshi Yamaguchi, Yutaka Urino, Michihiro Koibuchi:
Accelerating Parallel Sort on Tightly-Coupled FPGAs enabled by Onboard Si-Photonics Transceivers. OFC 2021: 1-3 - [c113]Naoya Niwa, Yoshiya Shikama, Hideharu Amano, Michihiro Koibuchi:
A Case for Low-Latency Network-on-Chip using Compression Routers. PDP 2021: 134-142 - [c112]Yoshiya Shikama, Ryuta Kawano, Hiroki Matsutani, Hideharu Amano, Yusuke Nagasaka, Naoto Fukumoto, Michihiro Koibuchi:
Low-Latency Low-Energy Memory-Cube Networks using Dual-Voltage Datapaths. PDP 2021: 143-147 - 2020
- [j46]Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
A Generalized Theory Based on the Turn Model for Deadlock-Free Irregular Networks. IEICE Trans. Inf. Syst. 103-D(1): 101-110 (2020) - [j45]Ke Cui, Michihiro Koibuchi:
Efficient Two-Opt Collective-Communication Operations on Low-Latency Random Network Topologies. IEICE Trans. Inf. Syst. 103-D(12): 2435-2443 (2020) - [j44]Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Traffic-Independent Multi-Path Routing for High-Throughput Data Center Networks. IEICE Trans. Inf. Syst. 103-D(12): 2471-2479 (2020) - [j43]Yao Hu, Michihiro Koibuchi:
Application Mapping and Scheduling of Uncertain Communication Patterns onto Non-Random and Random Network Topologies. IEICE Trans. Inf. Syst. 103-D(12): 2480-2493 (2020) - [c111]Takeo Hosomi, Ryota Yasudo, Michihiro Koibuchi, Shinji Shimojo:
Dual-Plane Isomorphic Hypercube Network. HPC Asia 2020: 73-80 - [c110]Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Yao Hu, Michihiro Koibuchi, Hideharu Amano:
Implementing a Multi-ejection Switch and Making the Use of Multiple Lanes in a Circuit-switched Multi-FPGA System. CANDAR (Workshops) 2020: 211-217 - [c109]Ke Cui, Michihiro Koibuchi:
A Diagonal Checksum Algorithm-Based Fault Tolerance for Parallel Matrix Multiplication. CANDAR (Workshops) 2020: 218-223 - [c108]Tomoya Itsubo, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani:
Accelerating Deep Learning using Multiple GPUs and FPGA-Based 10GbE Switch. PDP 2020: 102-109
2010 – 2019
- 2019
- [j42]Yao Hu, Michihiro Koibuchi:
Optimizing Slot Utilization and Network Topology for Communication Pattern on Circuit-Switched Parallel Computing Systems. IEICE Trans. Inf. Syst. 102-D(2): 247-260 (2019) - [j41]Michihiro Koibuchi:
Foreword. IEICE Trans. Inf. Syst. 102-D(12): 2280 (2019) - [j40]Ryota Yasudo, Michihiro Koibuchi, Koji Nakano, Hiroki Matsutani, Hideharu Amano:
Designing High-Performance Interconnection Networks with Host-Switch Graphs. IEEE Trans. Parallel Distributed Syst. 30(2): 315-330 (2019) - [c107]Michihiro Koibuchi, Lambert T. Leong, Tomohiro Totoki, Naoya Niwa, Hiroki Matsutani, Hideharu Amano, Henri Casanova:
Sparse 3-D NoCs with Inductive Coupling. DAC 2019: 49 - [c106]Yao Hu, Michihiro Koibuchi:
Diameter/ASPL-Based Mapping of Applications with Uncertain Communication over Random Interconnection Networks. ICPADS 2019: 249-258 - [c105]Michihiro Koibuchi, Ikki Fujiwara, Naoya Niwa, Tomohiro Totoki, Shoichi Hirasawa:
The Case for Water-Immersion Computer Boards. ICPP 2019: 29:1-29:10 - [c104]Yao Hu, Michihiro Koibuchi:
The Impact of Application Mapping on Non-Random and Random Network Topologies. ISPA/BDCloud/SocialCom/SustainCom 2019: 16-25 - [c103]Keita Azegami, Kazusa Musha, Kazuei Hironaka, Akram Ben Ahmed, Michihiro Koibuchi, Yao Hu, Hideharu Amano:
A STDM (Static Time Division Multiplexing) Switch on a Multi-FPGA System. MCSoC 2019: 328-333 - [c102]Michihiro Koibuchi:
Low-Latency Error-Prone Optical Networks for Fast Approximate Computation on High-End Datacenters. OECC/PSC 2019: 1-2 - 2018
- [j39]Koya Mitsuzuka, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani:
Proxy Responses by FPGA-Based Switch for MapReduce Stragglers. IEICE Trans. Inf. Syst. 101-D(9): 2258-2268 (2018) - [j38]Yao Hu, Michihiro Koibuchi:
Enhancing Job Scheduling on Inter-Rackscale Datacenters with Free-Space Optical Links. IEICE Trans. Inf. Syst. 101-D(12): 2922-2932 (2018) - [c101]Yao Hu, Michihiro Koibuchi:
The Impact of Job Mapping on Random Network Topology. CANDAR Workshops 2018: 79-85 - [c100]Ke Cui, Michihiro Koibuchi:
Performance Evaluation of Collective Communication on Random Network Topology. CANDAR Workshops 2018: 159-162 - [c99]Naoya Niwa, Tomohiro Totoki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
An Trace-Driven Performance Prediction Method for Exploring NoC Design Optimization. CANDAR Workshops 2018: 182-185 - [c98]Tomohiro Totoki, Michihiro Koibuchi, Hideharu Amano:
An Extension of A Temperature Modeling Tool HotSpot 6.0 for Castle-of-Chips Stacking. CANDAR Workshops 2018: 363-369 - [c97]Akram Ben Ahmed, Hayate Okuhara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Adaptive Body Bias Control Scheme for Ultra Low-Power Network-on-Chip Systems. MCSoC 2018: 146-153 - [c96]Truong Thao Nguyen, Hiroki Matsutani, Michihiro Koibuchi:
Low-Reliable Low-Latency Networks Optimized for HPC Parallel Applications. NCA 2018: 1-10 - [c95]Akram Ben Ahmed, Daichi Fujiki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
AxNoC: Low-power Approximate Network-on-Chips using Critical-Path Isolation. NOCS 2018: 6:1-6:8 - 2017
- [j37]Ryuta Kawano, Hiroshi Nakahara, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
A Novel Channel Assignment Method to Ensure Deadlock-Freedom for Deterministic Routing. IEICE Trans. Inf. Syst. 100-D(8): 1798-1806 (2017) - [j36]Ryuta Kawano, Hiroshi Nakahara, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
A Layout-Oriented Routing Method for Low-Latency HPC Networks. IEICE Trans. Inf. Syst. 100-D(12): 2796-2807 (2017) - [j35]Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tadao Nakamura:
Scalable Networks-on-Chip with Elastic Links Demarcated by Decentralized Routers. IEEE Trans. Computers 66(4): 702-716 (2017) - [j34]Nguyen T. Truong, Ikki Fujiwara, Michihiro Koibuchi, Khanh-Van Nguyen:
Distributed Shortcut Networks: Low-Latency Low-Degree Non-Random Topologies Targeting the Diameter and Cable Length Trade-Off. IEEE Trans. Parallel Distributed Syst. 28(4): 989-1001 (2017) - [c94]Thao-Nguyen Nguyen, Michihiro Koibuchi:
Cable-geometric error-prone approach for low-latency interconnection networks. CCGrid 2017: 699-702 - [c93]Michihiro Koibuchi, Tomohiro Totoki, Hiroki Matsutani, Hideharu Amano, Fabien Chaix, Ikki Fujiwara, Henri Casanova:
A Case for Uni-directional Network Topologies in Large-Scale Clusters. CLUSTER 2017: 178-187 - [c92]Koya Mitsuzuka, Ami Hayashi, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani:
In-switch approximate processing: Delayed tasks management for MapReduce applications. FPL 2017: 1-4 - [c91]Daichi Fujiki, Kiyo Ishii, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Henri Casanova, Michihiro Koibuchi:
High-Bandwidth Low-Latency Approximate Interconnection Networks. HPCA 2017: 469-480 - [c90]Takashi Kurimoto, Shigeo Urushidani, Hiroshi Yamada, Kenjiro Yamanaka, Motonori Nakamura, Shunji Abe, Kensuke Fukuda, Michihiro Koibuchi, Hiroki Takakura, Shigeki Yamada, Yusheng Ji:
SINET5: A low-latency and high-bandwidth backbone network for SDN/NFV Era. ICC 2017: 1-7 - [c89]Yao Hu, Hiroaki Hara, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi:
Towards Tightly-coupled Datacenter with Free-space Optical Links. ICCBDC 2017: 33-39 - [c88]Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
HiRy: An Advanced Theory on Design of Deadlock-Free Adaptive Routing for Arbitrary Topologies. ICPADS 2017: 664-673 - [c87]Ryota Yasudo, Michihiro Koibuchi, Koji Nakano, Hiroki Matsutani, Hideharu Amano:
Order/Radix Problem: Towards Low End-to-End Latency Interconnection Networks. ICPP 2017: 322-331 - [c86]Hiroshi Nakahara, Ryota Yasudo, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi:
3D Layout of Spidergon, Flattened Butterfly and Dragonfly on a Chip Stack with Inductive Coupling Through Chip Interface. ISPAN-FCST-ISCC 2017: 52-59 - [c85]Yao Hu, Tomohiro Kudoh, Michihiro Koibuchi:
A Case of Electrical Circuit Switched Interconnection Network for Parallel Computers. PDCAT 2017: 276-283 - 2016
- [j33]Michihiro Koibuchi, Ikki Fujiwara, Kiyo Ishii, Shu Namiki, Fabien Chaix, Hiroki Matsutani, Hideharu Amano, Tomohiro Kudoh:
Optical network technologies for HPC: computer-architects point of view. IEICE Electron. Express 13(6): 20152007 (2016) - [j32]Truong Thao Nguyen, Khanh-Van Nguyen, Ikki Fujiwara, Michihiro Koibuchi:
Layout-Conscious Expandable Topology for Low-Degree Interconnection Networks. IEICE Trans. Inf. Syst. 99-D(5): 1275-1284 (2016) - [j31]Akram Ben Ahmed, Hiroki Matsutani, Michihiro Koibuchi, Kimiyoshi Usami, Hideharu Amano:
Multi-Voltage Variable Pipeline Routers with the Same Clock Frequency for Low-Power Network-on-Chips Systems. IEICE Trans. Electron. 99-C(8): 909-917 (2016) - [j30]Yao Hu, Ikki Fujiwara, Michihiro Koibuchi:
Job Mapping and Scheduling on Free-Space Optical Networks. IEICE Trans. Inf. Syst. 99-D(11): 2694-2704 (2016) - [j29]Hiroshi Nakahara, Tomoya Ozaki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Novel Chip Stacking Methods to Extend Both Horizontally and Vertically for Many-Core Architectures with ThrouChip Interface. IEICE Trans. Inf. Syst. 99-D(12): 2871-2880 (2016) - [j28]Takahiro Kagami, Hiroki Matsutani, Michihiro Koibuchi, Yasuhiro Take, Tadahiro Kuroda, Hideharu Amano:
Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces. IEEE Trans. Very Large Scale Integr. Syst. 24(2): 493-506 (2016) - [c84]Ryuta Kawano, Hiroshi Nakahara, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
ACRO: Assignment of channels in reverse order to make arbitrary routing deadlock-free. ICIS 2016: 1-6 - [c83]Yao Hu, Ikki Fujiwara, Michihiro Koibuchi:
HPC Job Mapping over Reconfigurable Wireless Links. CCGrid 2016: 570-575 - [c82]Ryuta Kawano, Hiroshi Nakahara, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
LOREN: A Scalable Routing Method for Layout-Conscious Random Topologies. CANDAR 2016: 9-18 - [c81]Michihiro Koibuchi, Ikki Fujiwara, Fabien Chaix, Henri Casanova:
Towards Ideal Hop Counts in Interconnection Networks with Arbitrary Size. CANDAR 2016: 188-194 - [c80]Thanh-Chung Kieu, Khanh-Van Nguyen, Nguyen T. Truong, Ikki Fujiwara, Michihiro Koibuchi:
An Interconnection Network Exploiting Trade-Off between Routing Table Size and Path Length. CANDAR 2016: 666-670 - [c79]Satoshi Fujita, Koji Nakano, Michihiro Koibuchi, Ikki Fujiwara:
Deterministic Construction of Regular Geometric Graphs with Short Average Distance and Limited Edge Length. ICA3PP 2016: 295-309 - [c78]Koji Nakano, Daisuke Takafuji, Satoshi Fujita, Hiroki Matsutani, Ikki Fujiwara, Michihiro Koibuchi:
Randomly Optimized Grid Graph for Low-Latency Interconnection Networks. ICPP 2016: 340-349 - [c77]Takashi Kurimoto, Shigeo Urushidani, Hiroshi Yamada, Kenjiro Yamanaka, Motonori Nakamura, Shunji Abe, Kensuke Fukuda, Michihiro Koibuchi, Yusheng Ji, Hiroki Takakura, Shigeki Yamada:
A fully meshed backbone network for data-intensive sciences and SDN services. ICUFN 2016: 909-911 - [c76]Daichi Fujiki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Randomizing Packet Memory Networks for Low-Latency Processor-Memory Communication. PDP 2016: 168-175 - [c75]Fabien Chaix, Ikki Fujiwara, Michihiro Koibuchi:
Suitability of the Random Topology for HPC Applications. PDP 2016: 301-304 - [c74]Truong Thao Nguyen, Ikki Fujiwara, Michihiro Koibuchi:
A diagonal cabling approach to data center and HPC systems. SoICT 2016: 265-271 - 2015
- [j27]Shigeo Urushidani, Shunji Abe, Kenjiro Yamanaka, Kento Aida, Shigetoshi Yokoyama, Hiroshi Yamada, Motonori Nakamura, Kensuke Fukuda, Michihiro Koibuchi, Shigeki Yamada:
New Directions for a Japanese Academic Backbone Network. IEICE Trans. Inf. Syst. 98-D(3): 546-556 (2015) - [j26]Ahmed Shalaby, Ikki Fujiwara, Michihiro Koibuchi:
The Case for Network Coding for Collective Communication on HPC Interconnection Networks. IEICE Trans. Inf. Syst. 98-D(3): 661-670 (2015) - [j25]Ikki Fujiwara, Michihiro Koibuchi, Hiroki Matsutani, Henri Casanova:
Swap-And-Randomize: A Method for Building Low-Latency HPC Interconnects. IEEE Trans. Parallel Distributed Syst. 26(7): 2051-2060 (2015) - [c73]Seiichi Tade, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi:
A metamorphotic Network-on-Chip for various types of parallel applications. ASAP 2015: 98-105 - [c72]Ikki Fujiwara, Michihiro Koibuchi, Tomoya Ozaki, Hiroki Matsutani, Henri Casanova:
Augmenting low-latency HPC network with free-space optical links. HPCA 2015: 390-401 - [c71]Yao Hu, Ikki Fujiwara, Michihiro Koibuchi:
Enabling Ideal Job Mapping on Wireless Supercomputers and Datacenters. CANDAR 2015: 357-363 - [c70]Hiroshi Nakahara, Tomoya Ozaki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Expandable Chip Stacking Method for Many-core Architectures Consisting of Tiny Chips. MCSoC 2015: 41-48 - [c69]Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tadao Nakamura:
On-Chip Decentralized Routers with Balanced Pipelines for Avoiding Interconnect Bottleneck. NOCS 2015: 16:1-16:8 - [c68]Ryuta Kawano, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi:
Optimized Core-Links for Low-Latency NoCs. PDP 2015: 172-176 - [c67]Michihiro Koibuchi:
Singularity of Future Computer-System Networks. SoICT 2015: 3 - 2014
- [j24]Hao Zhang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Dynamic Power Consumption Optimization for Inductive-Coupling based Wireless 3D NoCs. IPSJ Trans. Syst. LSI Des. Methodol. 7: 27-36 (2014) - [j23]Satoshi Matsuoka, Hitoshi Sato, Osamu Tatebe, Michihiro Koibuchi, Ikki Fujiwara, Shuji Suzuki, Masanori Kakuta, Takashi Ishida, Yutaka Akiyama, Toyotaro Suzumura, Koji Ueno, Hiroki Kanezashi, Takemasa Miyoshi:
Extreme Big Data (EBD): Next Generation Big Data Infrastructure Technologies Towards Yottabyte/Year. Supercomput. Front. Innov. 1(2): 89-107 (2014) - [j22]Yasuhiro Take, Hiroki Matsutani, Daisuke Sasaki, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano:
3D NoC with Inductive-Coupling Links for Building-Block SiPs. IEEE Trans. Computers 63(3): 748-763 (2014) - [j21]Shigeo Urushidani, Michihiro Aoki, Kensuke Fukuda, Shunji Abe, Motonori Nakamura, Michihiro Koibuchi, Yusheng Ji, Shigeki Yamada:
Highly available network design and resource management of SINET4. Telecommun. Syst. 56(1): 33-47 (2014) - [c66]Hiroki Matsutani, Michihiro Koibuchi, Ikki Fujiwara, Takahiro Kagami, Yasuhiro Take, Tadahiro Kuroda, Paul Bogdan, Radu Marculescu, Hideharu Amano:
Low-latency wireless 3D NoCs via randomized shortcut chips. DATE 2014: 1-6 - [c65]Fabien Chaix, Ikki Fujiwara, Michihiro Koibuchi:
Darkfiber Planning for Extensible HPC Network Design under Uncertainties. CANDAR 2014: 382-387 - [c64]Nguyen T. Truong, Van K. Nguyen, Nhat T. X. Le, Ikki Fujiwara, Fabien Chaix, Michihiro Koibuchi:
Layout-aware expandable low-degree topology. ICPADS 2014: 462-470 - [c63]Ikki Fujiwara, Michihiro Koibuchi, Hiroki Matsutani, Henri Casanova:
Skywalk: A Topology for HPC Networks with Low-Delay Switches. IPDPS 2014: 263-272 - [c62]Ahmed Shalaby, Mohamed El-Sayed Ragab, Victor Goulart, Ikki Fujiwara, Michihiro Koibuchi:
Hierarchical Network Coding for Collective Communication on HPC Interconnects. PDP 2014: 98-102 - 2013
- [j20]Cisse Ahmadou Dit Adi, Michihiro Koibuchi, Masato Yoshimi, Hidetsugu Irie, Tsutomu Yoshinaga:
A Fully Optical Ring Network-on-Chip with Static and Dynamic Wavelength Allocation. IEICE Trans. Inf. Syst. 96-D(12): 2545-2554 (2013) - [c61]Hiroki Matsutani, Paul Bogdan, Radu Marculescu, Yasuhiro Take, Daisuke Sasaki, Hao Zhang, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano:
A case for wireless 3D NoCs for CMPs. ASP-DAC 2013: 23-28 - [c60]Hao Zhang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Dynamic power on/off method for 3D NoCs with wireless inductive-coupling links. COOL Chips 2013: 1-3 - [c59]Michihiro Koibuchi, Ikki Fujiwara, Hiroki Matsutani, Henri Casanova:
Layout-conscious random topologies for HPC off-chip interconnects. HPCA 2013: 484-495 - [c58]Michihiro Koibuchi:
Future Low-Latency Networks for High Performance Computing. CANDAR 2013: 22-23 - [c57]Daisuke Sasaki, Hao Zhang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
A Routing Strategy for Inductive-Coupling Based Wireless 3-D NoCs by Maximizing Topological Regularity. ICA3PP (2) 2013: 77-85 - [c56]Van K. Nguyen, Nhat T. X. Le, Ikki Fujiwara, Michihiro Koibuchi:
Distributed Shortcut Networks: Layout-Aware Low-Degree Topologies Exploiting Small-World Effect. ICPP 2013: 572-581 - [c55]Kalika Suksomboon, Saran Tarnoi, Yusheng Ji, Michihiro Koibuchi, Kensuke Fukuda, Shunji Abe, Motonori Nakamura, Michihiro Aoki, Shigeo Urushidani, Shigeki Yamada:
PopCache: Cache more or less based on content popularity for information-centric networking. LCN 2013: 236-243 - [c54]Takahiro Kagami, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Headfirst sliding routing: A time-based routing scheme for bus-NoC hybrid 3-D architecture. NOCS 2013: 1-8 - [i1]Tomohiro Yoneda, José Flich Cardo, Jiang Xu, Michihiro Koibuchi:
Many-cores and On-chip Interconnects (NII Shonan Meeting 2013-8). NII Shonan Meet. Rep. 2013 (2013) - 2012
- [j19]José Flich, Tor Skeie, Andres Mejia, Olav Lysne, Pedro López, Antonio Robles, José Duato, Michihiro Koibuchi, Tomas Rokicki, José Carlos Sancho:
A Survey and Evaluation of Topology-Agnostic Deterministic Routing Algorithms. IEEE Trans. Parallel Distributed Syst. 23(3): 405-425 (2012) - [c53]Kalika Suksomboon, Yusheng Ji, Michihiro Koibuchi, Kensuke Fukuda, Shunji Abe, Motonori Nakamura, Michihiro Aoki, Shigeo Urushidani, Shigeki Yamada:
On incentive-based inter-domain caching for content delivery in future internet architectures. AINTEC 2012: 1-8 - [c52]Hiroki Matsutani, Yuto Hirata, Michihiro Koibuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano:
A multi-Vdd dynamic variable-pipeline on-chip router for CMPs. ASP-DAC 2012: 407-412 - [c51]Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, D. Frank Hsu, Henri Casanova:
A case for random shortcut topologies for HPC interconnects. ISCA 2012: 177-188 - [c50]Yicheng Guan, Cisse Ahmadou Dit Adi, Takefumi Miyoshi, Michihiro Koibuchi, Hidetsugu Irie, Tsutomu Yoshinaga:
Throttling Control for Bufferless Routing in On-chip Networks. MCSoC 2012: 37-44 - [c49]Takeo Nakamura, Hiroki Matsutani, Michihiro Koibuchi, Kimiyoshi Usami, Hideharu Amano:
Fine-Grained Power Control Using A Multi-Voltage Variable Pipeline Router. MCSoC 2012: 59-66 - [c48]Ikki Fujiwara, Michihiro Koibuchi, Henri Casanova:
Cabinet Layout Optimization of Supercomputer Topologies for Shorter Cable Length. PDCAT 2012: 227-232 - 2011
- [j18]Cisse Ahmadou Dit Adi, Hiroki Matsutani, Michihiro Koibuchi, Hidetsugu Irie, Takefumi Miyoshi, Tsutomu Yoshinaga:
An Efficient Path Setup for a Hybrid Photonic Network-on-Chip. Int. J. Netw. Comput. 1(2): 244-259 (2011) - [j17]Yuri Nishikawa, Michihiro Koibuchi, Masato Yoshimi, Kenichi Miura, Hideharu Amano:
An analytical network performance model for SIMD processor CSX600 interconnects. J. Syst. Archit. 57(1): 146-159 (2011) - [j16]Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga:
Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors. IEEE Trans. Computers 60(6): 783-799 (2011) - [j15]Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano:
Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(4): 520-533 (2011) - [j14]Michihiro Koibuchi, Tomohiro Otsuka, Tomohiro Kudoh, Hideharu Amano:
A Switch-Tagged Routing Methodology for PC Clusters with VLAN Ethernet. IEEE Trans. Parallel Distributed Syst. 22(2): 217-230 (2011) - [c47]Kensuke Fukuda, Michihiro Aoki, Shunji Abe, Yusheng Ji, Michihiro Koibuchi, Motonori Nakamura, Shigeki Yamada, Shigeo Urushidani:
Impact of Tohoku earthquake on R&E network in Japan. SWID@CoNEXT 2011: 1:1-1:6 - [c46]Michihiro Koibuchi, Takafumi Watanabe, Atsushi Minamihata, Masahiro Nakao, Tomoyuki Hiroyasu, Hiroki Matsutani, Hideharu Amano:
Performance Evaluation of Power-Aware Multi-tree Ethernet for HPC Interconnects. ICNC 2011: 50-57 - [c45]Hiroki Matsutani, Yasuhiro Take, Daisuke Sasaki, Masayuki Kimura, Yuki Ono, Yukinori Nishiyama, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano:
A vertical bubble flow network using inductive-coupling for 3-D CMPs. NOCS 2011: 49-56 - [c44]Daihan Wang, Michihiro Koibuchi, Tomohiro Yoneda, Hiroki Matsutani, Hideharu Amano:
A Dynamic Link-Width Optimization for Network-on-Chip. RTCSA (2) 2011: 106-108 - [p2]Hiroki Matsutani, Michihiro Koibuchi, Hiroshi Nakamura, Hideharu Amano:
Run-Time Power-Gating Techniques for Low-Power On-Chip Networks. Low Power Networks-on-Chip 2011: 21-43 - [p1]Hiroki Matsutani, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano:
3-D NoC on Inductive Wireless Interconnect. 3D Integration for NoC-based SoC Architectures 2011: 225-248 - 2010
- [j13]Shigeo Urushidani, Kensuke Fukuda, Michihiro Koibuchi, Motonori Nakamura, Shunji Abe, Yusheng Ji, Michihiro Aoki, Shigeki Yamada:
Dynamic Resource Allocation and QoS Control Capabilities of the Japanese Academic Backbone Network. Future Internet 2(3): 295-307 (2010) - [c43]Cisse Ahmadou Dit Adi, Hiroki Matsutani, Michihiro Koibuchi, Hidetsugu Irie, Takefumi Miyoshi, Tsutomu Yoshinaga:
An Efficient Path Setup for a Photonic Network-on-Chip. ICNC 2010: 156-161 - [c42]Yasutsugu Nagatomi, Michihiro Koibuchi, Hideyuki Kawashima, Koichi Inoue, Hiroaki Nishi:
A Regular Expression Processor Embedded in Service-Friendly Router for Future Internet. ICPP Workshops 2010: 82-88 - [c41]Yuto Hirata, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
A variable-pipeline on-chip router optimized to traffic pattern. NoCArc@MICRO 2010: 57-62 - [c40]José Miguel Montañana Aliaga, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano:
Stabilizing Path Modification of Power-Aware On/Off Interconnection Networks. NAS 2010: 218-227 - [c39]Yuri Nishikawa, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano:
A Deadlock-Free Non-minimal Fully Adaptive Routing Using Virtual Cut-Through Switching. NAS 2010: 431-438 - [c38]Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano:
Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs. NOCS 2010: 61-68 - [c37]Tomoaki Makino, Koichi Inoue, Michihiro Koibuchi, Hideyuki Kawashima, Hiroaki Nishi:
Hardware Architecture for Supporting High-speed Database Insertion on Service-oriented Router for Future Internet. PDPTA 2010: 402-407
2000 – 2009
- 2009
- [j12]Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
A Link Removal Methodology for Application-Specific Networks-on-Chip on FPGAs. IEICE Trans. Inf. Syst. 92-D(4): 575-583 (2009) - [j11]Shigeo Urushidani, Shunji Abe, Yusheng Ji, Kensuke Fukuda, Michihiro Koibuchi, Motonori Nakamura, Shigeki Yamada, Kaori Shimizu, Rie Hayashi, Ichiro Inoue, Kohei Shiomoto:
Design of versatile academic infrastructure for multilayer network services. IEEE J. Sel. Areas Commun. 27(3): 253-267 (2009) - [j10]Jumpot Phuritatkul, Kien Nguyen, Michihiro Koibuchi, Yusheng Ji, Kensuke Fukuda, Shunji Abe, Jun Matsukata, Shigeo Urushidani, Shigeki Yamada:
Impact of QoS operations on an experimental testbed network. Simul. Model. Pract. Theory 17(3): 528-537 (2009) - [j9]Hiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, D. Frank Hsu, Hideharu Amano:
Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network. IEEE Trans. Parallel Distributed Syst. 20(8): 1126-1141 (2009) - [c36]Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga:
Prediction router: Yet another low latency on-chip router architecture. HPCA 2009: 367-378 - [c35]Shigeo Urushidani, Kensuke Fukuda, Yusheng Ji, Michihiro Koibuchi, Shunji Abe, Motonori Nakamura, Shigeki Yamada, Kaori Shimizu, Rie Hayashi, Ichiro Inoue, Kohei Shiomoto:
Implementation and Evaluation of Layer-1 Bandwidth-on-Demand Capabilities in SINET3. ICC 2009: 1-6 - [c34]José Miguel Montañana Aliaga, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano:
Balanced Dimension-Order Routing for k-ary n-cubes. ICPP Workshops 2009: 499-506 - [c33]Michihiro Koibuchi, Tomohiro Otsuka, Hiroki Matsutani, Hideharu Amano:
An on/off link activation method for low-power ethernet in PC clusters. IPDPS 2009: 1-11 - [c32]Tomoyuki Hiroyasu, Kozo Kawasaki, Michihiro Koibuchi, Shigeo Urushidani, Mitsunori Miki, Masato Yoshimi:
Efficient Scheduling Algorithms on Bandwidth Reservation Service of Internet Using Metaheuristics. ISDA 2009: 683-688 - [c31]Yuri Nishikawa, Michihiro Koibuchi, Masato Yoshimi, Akihiro Shitara, Kenichi Miura, Hideharu Amano:
Performance Analysis of ClearSpeed's CSX600 Interconnects. ISPA 2009: 203-210 - [c30]José Miguel Montañana Aliaga, Michihiro Koibuchi, Takafumi Watanabe, Tomoyuki Hiroyasu, Hiroki Matsutani, Hideharu Amano:
An On/Off Link Activation Method for Power Regulation in InfiniBand. PDPTA 2009: 289-295 - 2008
- [c29]Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Daihan Wang:
Run-time power gating of on-chip routers using look-ahead routing. ASP-DAC 2008: 55-60 - [c28]Takafumi Watanabe, Masahiro Nakao, Tomoyuki Hiroyasu, Tomohiro Otsuka, Michihiro Koibuchi:
Impact of topology and link aggregation on a PC cluster with Ethernet. CLUSTER 2008: 280-285 - [c27]Daihan Wang, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi:
A link removal methodology for Networks-on-Chip on reconfigurable systems. FPL 2008: 269-274 - [c26]Hiroki Matsutani, Michihiro Koibuchi, D. Frank Hsu, Hideharu Amano:
Three-Dimensional Layout of On-Chip Tree-Based Networks. ISPAN 2008: 281-288 - [c25]Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, Timothy Mark Pinkston:
A Lightweight Fault-Tolerant Mechanism for Network-on-Chip. NOCS 2008: 13-22 - [c24]Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang, Hideharu Amano:
Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks. NOCS 2008: 23-32 - 2007
- [j8]Shigeo Urushidani, Shunji Abe, Kensuke Fukuda, Jun Matsukata, Yusheng Ji, Michihiro Koibuchi, Shigeki Yamada:
Architectural Design of Next-Generation Science Information Network. IEICE Trans. Commun. 90-B(5): 1061-1070 (2007) - [j7]Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
A Port Combination Methodology for Application-Specific Networks-on-Chip on FPGAs. IEICE Trans. Inf. Syst. 90-D(12): 1914-1922 (2007) - [j6]Akiya Jouraku, Michihiro Koibuchi, Hideharu Amano:
An Effective Design of Deadlock-Free Routing Algorithms Based on 2D Turn Model for Irregular Networks. IEEE Trans. Parallel Distributed Syst. 18(3): 320-333 (2007) - [c23]Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
A Temporal Correlation Based Port Combination Methodology for Networks-on-chip on Reconfigurable Systems. FPL 2007: 383-388 - [c22]Shigeo Urushidani, Jun Matsukata, Kensuke Fukuda, Shunji Abe, Yusheng Ji, Michihiro Koibuchi, Shigeki Yamada, Kaori Shimizu, Tomonori Takeda, Ichiro Inoue, Kohei Shiomoto:
Layer-1 Bandwidth on Demand Services in SINET3. GLOBECOM 2007: 2286-2291 - [c21]Jumpot Phuritatkul, Kien Nguyen, Michihiro Koibuchi, Yusheng Ji:
Investigating QoS Performance on a Testbed Network. ICCCN 2007: 1267-1272 - [c20]Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Tightly-Coupled Multi-Layer Topologies for 3-D NoCs. ICPP 2007: 75 - [c19]Yuri Nishikawa, Michihiro Koibuchi, Masato Yoshimi, Kenichi Miura, Hideharu Amano:
Performance Improvement Methodology for ClearSpeed's CSX600. ICPP 2007: 77 - [c18]Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Performance, Cost, and Energy Evaluation of Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network. IPDPS 2007: 1-10 - 2006
- [j5]Michihiro Koibuchi, Kenichiro Anjo, Yutaka Yamada, Akiya Jouraku, Hideharu Amano:
A Simple Data Transfer Technique Using Local Address for Networks-on-Chips. IEEE Trans. Parallel Distributed Syst. 17(12): 1425-1437 (2006) - [c17]Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
A Virtual-Channel Free Mapping for Application-Specific On-Chip Torus Networks. PDCS 2006: 24-31 - [c16]Daihan Wang, Hiroki Matsutani, Masato Yoshimi, Michihiro Koibuchi, Hideharu Amano:
A Parametric Study of Scalable Interconnects on FPGAs. ERSA 2006: 130-135 - [c15]Tomohiro Otsuka, Michihiro Koibuchi, Tomohiro Kudoh, Hideharu Amano:
Switch-tagged VLAN Routing Methodology for PC Clusters with Ethernet. ICPP 2006: 479-486 - [c14]Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Enforcing Dimension-Order Routing in On-Chip Torus Networks Without Virtual Channels. ISPA 2006: 207-218 - 2005
- [j4]Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano:
MMLRU Selection Function: A Simple and Efficient Output Selection Function in Adaptive Routing. IEICE Trans. Inf. Syst. 88-D(1): 109-118 (2005) - [j3]Michihiro Koibuchi, Juan Carlos Martínez, José Flich, Antonio Robles, Pedro López, José Duato:
Enforcing in-order packet delivery in system area networks with adaptive routing. J. Parallel Distributed Comput. 65(10): 1223-1236 (2005) - [j2]Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano:
Path selection algorithm: the strategy for designing deterministic routing from alternative paths. Parallel Comput. 31(1): 117-130 (2005) - [j1]Michihiro Koibuchi, Konosuke Watanabe, Tomohiro Otsuka, Hideharu Amano:
Performance Evaluation of Deterministic Routings, Multicasts, and Topologies on RHiNET-2 Cluster. IEEE Trans. Parallel Distributed Syst. 16(8): 747-759 (2005) - [c13]Tomohiro Otsuka, Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano:
VLAN-Based Minimal Paths in PC Cluster with Ethernet on Mesh and Torus. ICPP 2005: 567-576 - [c12]Hiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, Akiya Jouraku, Hideharu Amano:
Non-Minimal Routing Strategy for Application-Specific Networks-on-Chips. ICPP Workshops 2005: 273-280 - [c11]Juan Carlos Martínez, José Flich, Antonio Robles, Pedro López, José Duato, Michihiro Koibuchi:
In-Order Packet Delivery in Interconnection Networks using Adaptive Routing. IPDPS 2005 - [c10]Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Destination Bundle: A Routing Table Reduction Technique for Distributed Routing on Dependable Networks-on-Chips. PDPTA 2005: 1343-1349 - 2004
- [c9]Yutaka Yamada, Hideharu Amano, Michihiro Koibuchi, Akiya Jouraku, Kenichiro Anjo, Katsunobu Nishimura:
Folded Fat H-Tree: An Interconnection Topology for Dynamically Reconfigurable Processor Array. EUC 2004: 301-311 - [c8]Kenichiro Anjo, Yutaka Yamada, Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano:
BLACK-BUS: A New Data-Transfer Technique Using Local Address on Networks-on-Chips. IPDPS 2004 - 2003
- [c7]Michihiro Koibuchi, Konosuke Watanabe, Kenichi Kono, Akiya Jouraku, Hideharu Amano:
Performance Evaluation of Routing Algorithms in RHiNET-2 Cluster. CLUSTER 2003: 395- - [c6]Michihiro Koibuchi, Akiya Jouraku, Konosuke Watanabe, Hideharu Amano:
Descending Layers Routing: A Deadlock-Free Deterministic Routing using Virtual Channels in System Area Networks with Irregular Topologies. ICPP 2003: 527- - 2002
- [c5]Akiya Jouraku, Michihiro Koibuchi, Hideharu Amano, Akira Funahashi:
Routing Algorithms Based on 2D Turn Model for Irregular Networks. ISPAN 2002: 289-294 - [c4]Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano:
The Impact of Path Selection Algorithm of Adaptive Routing for Implementing Deterministic Routing. PDPTA 2002: 1431-1437 - 2001
- [c3]Michihiro Koibuchi, Akiya Jouraku, Akira Funahashi, Hideharu Amano:
MMLRU Selection Function: An Output Selection Function on Adaptive Routing. PDCS 2001: 1-6 - [c2]Akira Funahashi, Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano:
The impact of output selection function on adaptive routing. CATA 2001: 241-246 - [c1]Michihiro Koibuchi, Akira Funahashi, Akiya Jouraku, Hideharu Amano:
L-Turn Routing: An Adaptive Routing in Irregular Networks. ICPP 2001: 383-392
Coauthor Index
[j55] [j54] [j52] [j50] [c124] [c121] [j49] [j48] [c119] [c117] [c113] [c112] [j46] [j44] [c110] [c108] [j40] [c107] [c103] [j39] [c99] [c98] [c97] [c95] [j37] [j36] [j35] [c93] [c92] [c91] [c89] [c88] [c87] [c86] [j33] [j31] [j29] [j28] [c84] [c82] [c76] [c73] [c70] [c69] [c68] [j24] [j22] [c66] [c61] [c60] [c57] [c54] [c52] [c51] [c49] [j17] [j16] [j15] [j14] [c46] [c45] [c44] [p2] [p1] [c41] [c40] [c39] [c38] [j12] [j9] [c36] [c34] [c33] [c31] [c30] [c29] [c27] [c26] [c25] [c24] [j7] [j6] [c23] [c20] [c19] [c18] [j5] [c17] [c16] [c15] [c14] [j4] [j2] [j1] [c13] [c12] [c10] [c9] [c8] [c7] [c6] [c5] [c4] [c3] [c2] [c1]
[j55] [c127] [i2] [j50] [c124] [j48] [c119] [c112] [j46] [j44] [c108] [j40] [c107] [j39] [c99] [c97] [c96] [c95] [j37] [j36] [j35] [c93] [c92] [c91] [c89] [c88] [c87] [c86] [j33] [j31] [j29] [j28] [c84] [c82] [c78] [c76] [j25] [c73] [c72] [c70] [c69] [c68] [j24] [j22] [c66] [c63] [c61] [c60] [c59] [c57] [c54] [c52] [c51] [c49] [j18] [j16] [j15] [c46] [c45] [c44] [p2] [p1] [c43] [c41] [c40] [c39] [c38] [j12] [j9] [c36] [c34] [c33] [c30] [c29] [c27] [c26] [c25] [c24] [j7] [c23] [c20] [c18] [c17] [c16] [c14] [c12] [c10]
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