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ORCID"Run-Time Power-Gating Techniques for Low-Power On-Chip Networks."
Hiroki Matsutani et al. (2011)
- Hiroki Matsutani, Michihiro Koibuchi, Hiroshi Nakamura
, Hideharu Amano:
Run-Time Power-Gating Techniques for Low-Power On-Chip Networks. Low Power Networks-on-Chip 2011: 21-43
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