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ORCIDEiichi Sano
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2010 – 2019
- 2019
[c9]Sayuri Yokoyama, Masayuki Ikebe, Yuri Kanazawa, Takahiro Ikegami, Prasoon Ambalathankandy
, Shota Hiramatsu, Eiichi Sano, Yuma Takida, Hiroaki Minamide:
A 32×32-Pixel 0.9THz Imager with Pixel-Parallel 12b VCO-Based ADC in 0.18μm CMOS. ISSCC 2019: 108-110- 2014
- [c8]Daisuke Uchida, Masayuki Ikebe, Junichi Motohisa, Eiichi Sano:
A 12-bit, 5.5-μW single-slope ADC using intermittent working TDC with multi-phase clock signals. ICECS 2014: 770-773 - 2013
- [c7]Toshiki Wada, Masayuki Ikebe, Eiichi Sano:
60-GHz, 9-µW wake-up receiver for short-range wireless communications. ESSCIRC 2013: 383-386 - 2012
- [c6]Kisu Kim, Masayuki Ikebe, Junichi Motohisa, Eiichi Sano:
A 11b 5.1µW multi-slope ADC with a TDC using multi-phase clock signals. ICECS 2012: 512-515 - 2011
- [c5]Akira Kondou, Masayuki Ikebe, Junichi Motohisa, Yoshihito Amemiya, Eiichi Sano:
A 0.6-4.5 GHz inductorless CMOS low noise amplifier with gyrator-C network. ICECS 2011: 326-329 - 2010
- [c4]Muung Shin, Masayuki Ikebe, Junichi Motohisa, Eiichi Sano:
Column parallel single-slope ADC with time to digital converter for CMOS imager. ICECS 2010: 863-866
2000 – 2009
- 2009
- [c3]Masayuki Ikebe, Daisuke Ueo, Kazuhiro Takahagi, Masaki Ohuno, Yusuke Takada, Eiichi Sano:
A 3.1-10.6 GHz RF CMOS circuits monolithically integrated with dipole antenna. ICECS 2009: 17-20 - [c2]Tomoki Iida, Tetsuya Asai, Eiichi Sano, Yoshihito Amemiya:
Offset cancellation with subthreshold-operated feedback circuit for fully differential amplifiers. ICECS 2009: 140-143 - 2007
- [j15]Mitsuhiro Hanabe, Yahya Moubarak Meziani, Taiichi Otsuji, Eiichi Sano, Tanemasa Asano:
Possibility of Terahertz Injection-Locked Oscillation in an InGaP/InGaAs/GaAs Two-Dimensional Plasmon-Resonant Photomixer. IEICE Trans. Electron. 90-C(5): 949-954 (2007) - [j14]Yukinobu Makihara, Masayuki Ikebe, Eiichi Sano:
Evaluation of Digitally Controlled PLL by Clock-Period Comparison. IEICE Trans. Electron. 90-C(6): 1307-1310 (2007) - 2006
- [j13]Eiichi Sano:
A chaotic wireless communication system based on collective synchronization among wireless nodes. IEICE Electron. Express 3(12): 262-268 (2006) - [j12]Koji Inafune, Eiichi Sano, Hideaki Matsuzaki, Toshihiko Kosugi, Takatomo Enoki:
W-Band Active Integrated Antenna Oscillator Based on Full-Wave Design Methodology and 0.1-µm Gate InP-Based HEMTs. IEICE Trans. Electron. 89-C(7): 954-958 (2006) - [j11]Mitsuhiro Hanabe, Takuya Nishimura, Masaki Miyamoto, Taiichi Otsuji, Eiichi Sano:
Structure-Sensitive Design for Wider Tunable Operation of Terahertz Plasmon-Resonant Photomixer. IEICE Trans. Electron. 89-C(7): 985-992 (2006) - [j10]Takuya Nishimura, Mitsuhiro Hanabe, Masaki Miyamoto, Taiichi Otsuji, Eiichi Sano:
Terahertz Frequency Multiplier Operation of Two Dimensional Plasmon Resonant Photomixer. IEICE Trans. Electron. 89-C(7): 1005-1011 (2006) - 2004
- [j9]Eiichi Sano, Koji Inafune, Masamichi Akazawa:
RF CMOS inductor shielded by a high-impedance surface. IEICE Electron. Express 1(8): 233-236 (2004) - [j8]Hideyuki Nosaka, Eiichi Sano, Kiyoshi Ishii, Minoru Ida, Kenji Kurishima, Shoji Yamahata, Tsugumichi Shibata, Hiroyuki Fukuyama, Mikio Yoneyama, Takatomo Enoki, Masahiro Muraguchi:
A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with a robust lock detector. IEEE J. Solid State Circuits 39(8): 1361-1365 (2004) - 2002
- [j7]Kiyoshi Ishii, Hideyuki Nosaka, Hiroki Nakajima, Kenji Kurishima, Minoru Ida, Noriyuki Watanabe, Yasurou Yamane, Eiichi Sano, Takatomo Enoki:
Low-power 1: 16 DEMUX and one-chip CDR with 1: 4 DEMUX using InP-InGaAs heterojunction bipolar transistors. IEEE J. Solid State Circuits 37(9): 1146-1151 (2002) - 2001
- [j6]Eiichi Sano:
High-speed lightwave communication ICs based on III-V compound semiconductors. IEEE Commun. Mag. 39(1): 154-158 (2001) - [j5]Kimikazu Sano, Koichi Murata, Taiichi Otsuji, Tomoyuki Akeyoshi, Naofumi Shimizu, Eiichi Sano:
An 80-Gb/s optoelectronic delayed flip-flop IC using resonant tunneling diodes and uni-traveling-carrier photodiode. IEEE J. Solid State Circuits 36(2): 281-289 (2001)
1990 – 1999
- 1999
- [c1]Shunji Kimura, Taiichi Otsuji, Hiroyuki Kikuchi, Koichi Murata, Eiichi Sano:
Circuit design technologies for high-speed lightwave communications beyond 40 Gbit/s. ISCAS (2) 1999: 488-491 - 1997
- [j4]Taiichi Otsuji, Mikio Yoneyama, Koichi Murata, Eiichi Sano:
A super-dynamic flip-flop circuit for broad-band applications up to 24 Gb/s utilizing production-level 0.2-μm GaAs MESFETs. IEEE J. Solid State Circuits 32(9): 1357-1362 (1997) - [j3]Taiichi Otsuji, Yuhki Imai, Eiichi Sano, Shunji Kimura, Satoshi Yamaguchi, Mikio Yoneyama, Takatomo Enoki, Yohtaro Umeda:
40-Gb/s ICs for future lightwave communications systems. IEEE J. Solid State Circuits 32(9): 1363-1370 (1997) - 1995
- [j2]Koichi Murata, Taiichi Otsuji, Eiichi Sano, Masanobu Ohhata, Minoru Togashi, Masao Suzuki:
A novel high-speed latching operation flip-flop (HLO-FF) circuit and its application to a 19-Gb/s decision circuit using a 0.2-μm GaAs MESFET. IEEE J. Solid State Circuits 30(10): 1101-1108 (1995)
1980 – 1989
- 1988
- [j1]Eiichi Sano, Tsuneo Tsukahara, Atsushi Iwata:
Performance limits of mixed analog/digital circuits with scaled MOSFETs. IEEE J. Solid State Circuits 23(4): 942-949 (1988)
Coauthor Index
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