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ORCIDTakatomo Enoki
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2000 – 2009
- 2009
[j16]Toshihiko Kosugi, Hiroki Sugiyama
, Koichi Murata, Hiroyuki Takahashi, Akihiko Hirata, Naoya Kukutsu, Yuichi Kado, Takatomo Enoki:
A 125-GHz 140-mW InGaAs/InP composite-channel HEMT MMIC power amplifier module. IEICE Electron. Express 6(24): 1764-1768 (2009)- [j15]Yoshino K. Fukai, Kenji Kurishima, Norihide Kashio, Minoru Ida, Shoji Yamahata, Takatomo Enoki:
Emitter-metal-related degradation in InP-based HBTs operating at high current density and its suppression by refractory metal. Microelectron. Reliab. 49(4): 357-364 (2009) - 2006
- [j14]Takatomo Enoki:
Special Section on Heterostructure Microelectronics with TWHM2005. IEICE Trans. Electron. 89-C(7): 873 (2006) - [j13]Hideaki Matsuzaki, Takashi Maruyama, Takatomo Enoki, Masami Tokumitsu:
Novel Fabrication Technology for High Yield Sub-100-nm-Gate InP-Based HEMTs. IEICE Trans. Electron. 89-C(7): 949-953 (2006) - [j12]Koji Inafune, Eiichi Sano, Hideaki Matsuzaki, Toshihiko Kosugi, Takatomo Enoki:
W-Band Active Integrated Antenna Oscillator Based on Full-Wave Design Methodology and 0.1-µm Gate InP-Based HEMTs. IEICE Trans. Electron. 89-C(7): 954-958 (2006) - 2005
- [j11]Kiyoshi Ishii, Hideyuki Nosaka, Kimikazu Sano, Koichi Murata, Minoru Ida, Kenji Kurishima, Michihiro Hirata, Tsugumichi Shibata, Takatomo Enoki:
High-bit-rate low-power decision circuit using InP-InGaAs HBT technology. IEEE J. Solid State Circuits 40(7): 1583-1588 (2005) - 2004
- [j10]Hideaki Matsuzaki, Kimikazu Sano, Takatomo Enoki:
Low-power and High-speed SCFL-inverter Using Pseudomorphic InGaAs Channel High Electron Mobility Transistors. IEICE Electron. Express 1(2): 24-28 (2004) - [j9]Hideaki Matsuzaki, Hiroki Sugiyama, Haruki Yokoyama, Takashi Kobayashi, Takatomo Enoki:
Suppression of short-channel effect in pseudomorphic In0.25Al0.75P/In0.75Ga0.25As high electron mobility transistors. IEICE Electron. Express 1(11): 292-297 (2004) - [j8]Koichi Murata, Kimikazu Sano, Hiroto Kitabayashi, Suehiro Sugitani, Hirohiko Sugahara, Takatomo Enoki:
100-Gb/s multiplexing and demultiplexing IC operations in InP HEMT technology. IEEE J. Solid State Circuits 39(1): 207-213 (2004) - [j7]Hideyuki Nosaka, Eiichi Sano, Kiyoshi Ishii, Minoru Ida, Kenji Kurishima, Shoji Yamahata, Tsugumichi Shibata, Hiroyuki Fukuyama, Mikio Yoneyama, Takatomo Enoki, Masahiro Muraguchi:
A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with a robust lock detector. IEEE J. Solid State Circuits 39(8): 1361-1365 (2004) - [j6]Hiroyuki Fukuyama, Kimikazu Sano, Koichi Murata, Hiroto Kitabayashi, Yasuro Yamane, Takatomo Enoki, Hirohiko Sugahara:
Photoreceiver module using an InP HEMT transimpedance amplifier for over 40 gb/s. IEEE J. Solid State Circuits 39(10): 1690-1696 (2004) - 2003
- [j5]Hideyuki Nosaka, Kiyoshi Ishii, Takatomo Enoki, Tsugumichi Shibata:
A 10-Gb/s data-pattern independent clock and data recovery circuit with a two-mode phase comparator. IEEE J. Solid State Circuits 38(2): 192-197 (2003) - [j4]Kimikazu Sano, Koichi Murata, Suehiro Sugitani, Hirohiko Sugahara, Takatomo Enoki:
50-Gb/s 4-b multiplexer/demultiplexer chip set using InP HEMTs. IEEE J. Solid State Circuits 38(9): 1504-1511 (2003) - 2002
- [j3]Kiyoshi Ishii, Hideyuki Nosaka, Hiroki Nakajima, Kenji Kurishima, Minoru Ida, Noriyuki Watanabe, Yasurou Yamane, Eiichi Sano, Takatomo Enoki:
Low-power 1: 16 DEMUX and one-chip CDR with 1: 4 DEMUX using InP-InGaAs heterojunction bipolar transistors. IEEE J. Solid State Circuits 37(9): 1146-1151 (2002)
1990 – 1999
- 1998
- [j2]Taiichi Otsuji, Koichi Murata, Takatomo Enoki, Yohtaro Umeda:
An 80-Gbit/s multiplexer IC using InAlAs/InGaAs/InP HEMTs. IEEE J. Solid State Circuits 33(9): 1321-1327 (1998) - 1997
- [j1]Taiichi Otsuji, Yuhki Imai, Eiichi Sano, Shunji Kimura, Satoshi Yamaguchi, Mikio Yoneyama, Takatomo Enoki, Yohtaro Umeda:
40-Gb/s ICs for future lightwave communications systems. IEEE J. Solid State Circuits 32(9): 1363-1370 (1997)
Coauthor Index
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