"A 10-Gb/s data-pattern independent clock and data recovery circuit with a ..."

Hideyuki Nosaka et al. (2003)

> Home

Details and statistics

DOI: 10.1109/JSSC.2002.807408

access: closed

type: Journal Article

metadata version: 2023-09-30

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jssc/NosakaIES03
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jssc/NosakaIES03
Hideyuki Nosaka, Kiyoshi Ishii, Takatomo Enoki, Tsugumichi Shibata:
A 10-Gb/s data-pattern independent clock and data recovery circuit with a two-mode phase comparator. IEEE J. Solid State Circuits 38(2): 192-197 (2003)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.