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ORCIDSanroku Tsukamoto
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2010 – 2019
- 2017
[j13]Sanroku Tsukamoto:
Advances in Analog-to-Digital Converters over the Last Decade. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(2): 524-533 (2017)- [c11]Satoshi Matsubara, Hirotaka Tamura, Motomu Takatsu, Danny Yoo, Behraz Vatankhahghadim
, Hironobu Yamasaki, Toshiyuki Miyazawa, Sanroku Tsukamoto, Yasuhiro Watanabe, Kazuya Takemoto, Ali Sheikholeslami:
Ising-Model Optimizer with Parallel-Trial Bit-Sieve Engine. CISIS 2017: 432-438 - 2015
- [j12]Kentaro Yoshioka, Ryo Saito, Takumi Danjo, Sanroku Tsukamoto, Hiroki Ishikuro:
Dynamic Architecture and Frequency Scaling in 0.8-1.2 GS/s 7 b Subranging ADC. IEEE J. Solid State Circuits 50(4): 932-945 (2015) - 2014
- [j11]Sanroku Tsukamoto, Masaya Miyahara, Akira Matsuzawa:
A 7-bit 1-GS/s Flash ADC with Background Calibration. IEICE Trans. Electron. 97-C(4): 298-307 (2014) - [j10]Takumi Danjo, Masato Yoshioka, Masayuki Isogai, Masanori Hoshino, Sanroku Tsukamoto:
A 6-bit, 1-GS/s, 9.9-mW, Interpolated Subranging ADC in 65-nm CMOS. IEEE J. Solid State Circuits 49(3): 673-682 (2014) - [c10]Kentaro Yoshioka, Ryo Saito, Takumi Danjo, Sanroku Tsukamoto, Hiroki Ishikuro:
7-bit 0.8-1.2GS/s Dynamic Architecture and Frequency Scaling subrange ADC with binary-search/flash Live Configuring Technique. VLSIC 2014: 1-2 - 2013
- [j9]Yoshiyasu Doi, Takayuki Shibasaki, Takumi Danjo, Win Chaivipas, Takushi Hashida, Hiroki Miyaoka, Masanori Hoshino, Yoichi Koyanagi, Takuji Yamamoto, Sanroku Tsukamoto, Hirotaka Tamura:
A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process. IEEE J. Solid State Circuits 48(12): 3258-3267 (2013) - [c9]Yoshiyasu Doi, Takayuki Shibasaki, Takumi Danjo, Win Chaivipas, Takushi Hashida, Hiroki Miyaoka, Masanori Hoshino, Yoichi Koyanagi, Takuji Yamamoto, Sanroku Tsukamoto, Hirotaka Tamura:
32Gb/s data-interpolator receiver with 2-tap DFE in 28nm CMOS. ISSCC 2013: 36-37 - 2012
- [j8]Xiaolei Zhu, Yanfei Chen, Sanroku Tsukamoto, Tadahiro Kuroda:
A 9-bit 100 MS/s SAR ADC with Digitally Assisted Background Calibration. IEICE Trans. Electron. 95-C(6): 1026-1034 (2012) - [c8]Takumi Danjo, Masato Yoshioka, Masayuki Isogai, Masanori Hoshino, Sanroku Tsukamoto:
A 6b, 1GS/s, 9.9mW interpolated subranging ADC in 65nm CMOS. VLSI-DAT 2012: 1-4 - [c7]Xiaolei Zhu, Yanfei Chen, Sanroku Tsukamoto, Tadahiro Kuroda:
A 9-bit 100MS/s tri-level charge redistribution SAR ADC with asymmetric CDAC array. VLSI-DAT 2012: 1-4 - 2010
- [j7]Yanfei Chen, Xiaolei Zhu, Hirotaka Tamura, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Masato Yoshioka, Kiyoshi Ishikawa, Takeshi Takayama, Junji Ogawa, Sanroku Tsukamoto, Tadahiro Kuroda:
Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC. IEICE Trans. Electron. 93-C(3): 295-302 (2010) - [j6]Xiaolei Zhu, Yanfei Chen, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Hirotaka Tamura, Sanroku Tsukamoto, Tadahiro Kuroda:
A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(12): 2456-2462 (2010) - [j5]Yanfei Chen, Sanroku Tsukamoto, Tadahiro Kuroda:
A 9-bit 100-MS/s 1.46-mW Tri-Level SAR ADC in 65 nm CMOS. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(12): 2600-2608 (2010) - [j4]Masato Yoshioka, Kiyoshi Ishikawa, Takeshi Takayama, Sanroku Tsukamoto:
A 10-b 50-MS/s 820- μ W SAR ADC With On-Chip Digital Calibration. IEEE Trans. Biomed. Circuits Syst. 4(6): 410-416 (2010) - [c6]Masato Yoshioka, Kiyoshi Ishikawa, Takeshi Takayama, Sanroku Tsukamoto:
A 10b 50MS/s 820µW SAR ADC with on-chip digital calibration. ISSCC 2010: 384-385
2000 – 2009
- 2009
- [c5]Xiaolei Zhu, Sanroku Tsukamoto, Tadahiro Kuroda:
A 1 GHz CMOS comparator with dynamic offset control technique. ASP-DAC 2009: 103-104 - [c4]Yanfei Chen, Xiaolei Zhu, Hirotaka Tamura, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Masato Yoshioka, Kiyoshi Ishikawa, Takeshi Takayama, Junji Ogawa, Sanroku Tsukamoto, Tadahiro Kuroda:
Split capacitor DAC mismatch calibration in successive approximation ADC. CICC 2009: 279-282 - [c3]Masashi Kijima, Kenji Ito, Kuniyoshi Kamei, Sanroku Tsukamoto:
A 6b 3GS/s flash ADC with background calibration. CICC 2009: 283-286 - 2008
- [j3]Sanroku Tsukamoto, Shen-Iuan Liu, Stefan Heinen, Roland Thewes, Jri Lee:
Introduction to the Special Issue on the 2008 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits 43(12): 2587-2591 (2008) - [c2]Xiaolei Zhu, Yanfei Chen, Masaya Kibune, Yasumoto Tomita, Takayuki Hamada, Hirotaka Tamura, Sanroku Tsukamoto, Tadahiro Kuroda:
A dynamic offset control technique for comparator design in scaled CMOS technology. CICC 2008: 495-498 - 2007
- [c1]Masato Yoshioka, Masahiro Kudo, Toshihiko Mori, Sanroku Tsukamoto:
A 0.8V 10b 8OMS/s 6.5mW Pipelined ADC with Regulated Overdrive Voltage Biasing. ISSCC 2007: 452-614
1990 – 1999
- 1998
- [j2]Sanroku Tsukamoto, William G. Schofield, Toshiaki Endo:
A CMOS 6-b, 400-MSample/s ADC with error correction. IEEE J. Solid State Circuits 33(12): 1939-1947 (1998) - 1996
- [j1]Sanroku Tsukamoto, I. Dedic, Toshiaki Endo, K. y. Kikuta, K. Goto, O. Kobayashi:
A CMOS 6-b, 200 MSample/s, 3 V-supply A/D converter for a PRML read channel LSI. IEEE J. Solid State Circuits 31(11): 1831-1836 (1996)
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