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ORCIDJri Lee
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2010 – 2019
- 2017
[c23]Pen-Jui Peng
, Jeng-Feng Li, Li-Yang Chen, Jri Lee:
6.1 A 56Gb/s PAM-4/NRZ transceiver in 40nm CMOS. ISSCC 2017: 110-111- 2015
- [j22]Ping-Chuan Chiang, Jhih-Yu Jiang, Hao-Wei Hung, Chin-Yang Wu, Gaun-Sing Chen, Jri Lee:
4×25 Gb/s Transceiver With Optical Front-end for 100 GbE System in 65 nm CMOS Technology. IEEE J. Solid State Circuits 50(2): 573-585 (2015) - [j21]Pen-Jui Peng, Pang-Ning Chen, Chiro Kao, Yu-Lun Chen, Jri Lee:
A 94 GHz 3D Image Radar Engine With 4TX/4RX Beamforming Scan Technique in 65 nm CMOS Technology. IEEE J. Solid State Circuits 50(3): 656-668 (2015) - [j20]Jri Lee, Ping-Chuan Chiang, Pen-Jui Peng, Li-Yang Chen, Chih-Chi Weng:
Design of 56 Gb/s NRZ and PAM4 SerDes Transceivers in CMOS Technologies. IEEE J. Solid State Circuits 50(9): 2061-2073 (2015) - [c22]Li-Yang Chen, Pen-Jui Peng, Chiro Kao, Yu-Lun Chen, Jri Lee:
CW/FMCW/pulse radar engines for 24/26GHz multi-standard applications in 65nm CMOS. A-SSCC 2015: 1-4 - [c21]Jri Lee, Ping-Chuan Chiang, Chih-Chi Weng:
56Gb/s PAM4 and NRZ SerDes transceivers in 40nm CMOS. VLSIC 2015: 118- - 2014
- [c20]Guan-Sing Chen, Chin-Yang Wu, Chen-Lun Lin, Hao-Wei Hung, Jri Lee:
Fully-integrated 40-Gb/s pulse pattern generator and bit-error-rate tester chipsets in 65-nm CMOS technology. A-SSCC 2014: 109-112 - [c19]Ping-Chuan Chiang, Hao-Wei Hung, Hsiang-Yun Chu, Guan-Sing Chen, Jri Lee:
2.3 60Gb/s NRZ and PAM4 transmitters for 400GbE in 65nm CMOS. ISSCC 2014: 42-43 - [c18]Yu-Lun Chen, Chiro Kao, Pen-Jui Peng, Jri Lee:
A 94GHz duobinary keying wireless transceiver in 65nm CMOS. VLSIC 2014: 1-2 - 2013
- [c17]Jhih-Yu Jiang, Ping-Chuan Chiang, Hao-Wei Hung, Chen-Lun Lin, Ty Yoon, Jri Lee:
100Gb/s ethernet chipsets in 65nm CMOS technology. ISSCC 2013: 120-121 - [c16]Pang-Ning Chen, Pen-Jui Peng, Chiro Kao, Yu-Lun Chen, Jri Lee:
A 94GHz 3D-image radar engine with 4TX/4RX beamforming scan technique in 65nm CMOS. ISSCC 2013: 146-147 - 2012
- [j19]Ming-Shuan Chen, Yu-Nan Shih, Chen-Lun Lin, Hao-Wei Hung, Jri Lee:
A Fully-Integrated 40-Gb/s Transceiver in 65-nm CMOS Technology. IEEE J. Solid State Circuits 47(3): 627-640 (2012) - 2011
- [j18]Shih-Jou Huang, Yu-Ching Yeh, Huaide Wang, Pang-Ning Chen, Jri Lee:
W-Band BPSK and QPSK Transceivers With Costas-Loop Carrier Recovery in 65-nm CMOS Technology. IEEE J. Solid State Circuits 46(12): 3033-3046 (2011) - [c15]Ming-Shuan Chen, Yu-Nan Shih, Chen-Lun Lin, Hao-Wei Hung, Jri Lee:
A 40Gb/s TX and RX chip set in 65nm CMOS. ISSCC 2011: 146-148 - [c14]Shih-Jou Huang, Yu-Ching Yeh, Huaide Wang, Pang-Ning Chen, Jri Lee:
An 87GHz QPSK transceiver with costas-loop carrier recovery in 65nm CMOS. ISSCC 2011: 168-170 - [c13]Jri Lee:
Tutorial: "Design of high-speed wireline transceivers". SoCC 2011: 353 - 2010
- [j17]Jri Lee, Yentso Chen, Yenlin Huang:
A Low-Power Low-Cost Fully-Integrated 60-GHz Transceiver System With OOK Modulation and On-Board Antenna Assembly. IEEE J. Solid State Circuits 45(2): 264-275 (2010) - [j16]Huaide Wang, Jri Lee:
A 21-Gb/s 87-mW Transceiver With FFE/DFE/Analog Equalizer in 65-nm CMOS Technology. IEEE J. Solid State Circuits 45(4): 909-920 (2010) - [j15]Ke-Chung Wu, Jri Lee:
A 2 , ˟, 25-Gb/s Receiver With 2: 5 DMUX for 100-Gb/s Ethernet. IEEE J. Solid State Circuits 45(11): 2421-2432 (2010) - [j14]Jri Lee, Yi-An Li, Meng-Hsiung Hung, Shih-Jou Huang:
A Fully-Integrated 77-GHz FMCW Radar Transceiver in 65-nm CMOS Technology. IEEE J. Solid State Circuits 45(12): 2746-2756 (2010) - [c12]Yi-An Li, Meng-Hsiung Hung, Shih-Jou Huang, Jri Lee:
A fully integrated 77GHz FMCW radar system in 65nm CMOS. ISSCC 2010: 216-217 - [c11]Ke-Chung Wu, Jri Lee:
A 2×25Gb/s deserializer with 2∶5 DMUX for 100Gb/s ethernet applications. ISSCC 2010: 374-375
2000 – 2009
- 2009
- [j13]Jri Lee, Huaide Wang:
Study of Subharmonically Injection-Locked PLLs. IEEE J. Solid State Circuits 44(5): 1539-1553 (2009) - [j12]Jri Lee, Ke-Chung Wu:
A 20-Gb/s Full-Rate Linear Clock and Data Recovery Circuit With Automatic Frequency Acquisition. IEEE J. Solid State Circuits 44(12): 3590-3602 (2009) - [c10]Jri Lee, Huaide Wang, Wen-Tsao Chen, Yung-Pin Lee:
Subharmonically injection-locked PLLs for ultra-low-noise clock generation. ISSCC 2009: 92-93 - [c9]Jri Lee, Yenlin Huang, Yentso Chen, Hsinchia Lu, Chiajung Chang:
A low-power fully integrated 60GHz transceiver system with OOK modulation and on-board antenna assembly. ISSCC 2009: 316-317 - [c8]Jri Lee, Ke-Chung Wu:
A 20Gb/s full-rate linear CDR circuit with automatic frequency acquisition. ISSCC 2009: 366-367 - 2008
- [j11]Jri Lee, Mingchung Liu:
A 20-Gb/s Burst-Mode Clock and Data Recovery Circuit Using Injection-Locking Technique. IEEE J. Solid State Circuits 43(3): 619-630 (2008) - [j10]Jri Lee, Mingchung Liu, Huaide Wang:
A 75-GHz Phase-Locked Loop in 90-nm CMOS Technology. IEEE J. Solid State Circuits 43(6): 1414-1426 (2008) - [j9]Jri Lee, Ming-Shuan Chen, Huaide Wang:
Design and Comparison of Three 20-Gb/s Backplane Transceivers for Duobinary, PAM4, and NRZ Data. IEEE J. Solid State Circuits 43(9): 2120-2133 (2008) - [j8]Sanroku Tsukamoto, Shen-Iuan Liu, Stefan Heinen, Roland Thewes, Jri Lee:
Introduction to the Special Issue on the 2008 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits 43(12): 2587-2591 (2008) - [c7]Jri Lee, Ming-Shuan Chen, Huaide Wang:
A 20Gb/s Duobinary Transceiver in 90nm CMOS. ISSCC 2008: 102-103 - 2007
- [c6]Jri Lee, Mingchung Liu:
A 20Gb/s Burst-Mode CDR Circuit Using Injection-Locking Technique. ISSCC 2007: 46-586 - [c5]John T. Stonick, Jri Lee:
Gigabit CDRs Equalizers. ISSCC 2007: 220-221 - [c4]Jri Lee:
A 75-GHz PLL in 90-nm CMOS Technology. ISSCC 2007: 432-613 - [c3]Jri Lee, Huaide Wang:
A 20Gb/s Broadband Transmitter with Auto-Configuration Technique. ISSCC 2007: 444-614 - 2006
- [j7]Jri Lee:
A 3-to-8-GHz fast-hopping frequency synthesizer in 0.18-μm CMOS technology. IEEE J. Solid State Circuits 41(3): 566-573 (2006) - [j6]Jri Lee:
High-speed circuit designs for transmitters in broadband data links. IEEE J. Solid State Circuits 41(5): 1004-1015 (2006) - [j5]Jri Lee:
A 20-Gb/s Adaptive Equalizer in 0.13-$muhbox m$CMOS Technology. IEEE J. Solid State Circuits 41(9): 2058-2066 (2006) - [c2]Jri Lee:
A 20Gb/s Adaptive Equalizer in 0.13µm CMOS Technology. ISSCC 2006: 273-282 - 2005
- [j4]Jri Lee, Behzad Razavi:
Correction to "A 40-Gb/s Clock and Data Recovery Circuit in 0.18μm CMOS Technology". IEEE J. Solid State Circuits 40(2): 559 (2005) - 2004
- [j3]Jri Lee, Behzad Razavi:
A 40-GHz frequency divider in 0.18-μm CMOS technology. IEEE J. Solid State Circuits 39(4): 594-601 (2004) - [j2]Jri Lee, Kenneth S. Kundert, Behzad Razavi:
Analysis and modeling of bang-bang clock and data recovery circuits. IEEE J. Solid State Circuits 39(9): 1571-1580 (2004) - 2003
- [j1]Jri Lee, Behzad Razavi:
A 40-Gb/s clock and data recovery circuit in 0.18-μm CMOS technology. IEEE J. Solid State Circuits 38(12): 2181-2190 (2003) - [c1]Jri Lee, Kenneth S. Kundert, Behzad Razavi:
Modeling of jitter in bang-bang clock and data recovery circuits. CICC 2003: 711-714
Coauthor Index
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