"Fully-integrated 40-Gb/s pulse pattern generator and bit-error-rate tester ..."

Guan-Sing Chen et al. (2014)

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DOI: 10.1109/ASSCC.2014.7008872

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-24

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Guan-Sing Chen, Chin-Yang Wu, Chen-Lun Lin, Hao-Wei Hung, Jri Lee:
Fully-integrated 40-Gb/s pulse pattern generator and bit-error-rate tester chipsets in 65-nm CMOS technology. A-SSCC 2014: 109-112

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