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ORCIDTakumi Danjo
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Journal Articles
- 2015
[j3]Kentaro Yoshioka
, Ryo Saito, Takumi Danjo, Sanroku Tsukamoto, Hiroki Ishikuro:
Dynamic Architecture and Frequency Scaling in 0.8-1.2 GS/s 7 b Subranging ADC. IEEE J. Solid State Circuits 50(4): 932-945 (2015)- 2014
- [j2]Takumi Danjo, Masato Yoshioka, Masayuki Isogai, Masanori Hoshino, Sanroku Tsukamoto:
A 6-bit, 1-GS/s, 9.9-mW, Interpolated Subranging ADC in 65-nm CMOS. IEEE J. Solid State Circuits 49(3): 673-682 (2014) - 2013
- [j1]Yoshiyasu Doi, Takayuki Shibasaki, Takumi Danjo, Win Chaivipas, Takushi Hashida, Hiroki Miyaoka, Masanori Hoshino, Yoichi Koyanagi, Takuji Yamamoto, Sanroku Tsukamoto, Hirotaka Tamura:
A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process. IEEE J. Solid State Circuits 48(12): 3258-3267 (2013)
Conference and Workshop Papers
- 2021
- [c6]Steven Farrell, Murali Emani, Jacob Balma, Lukas Drescher, Aleksandr Drozd, Andreas Fink, Geoffrey C. Fox, David Kanter, Thorsten Kurth, Peter Mattson, Dawei Mu, Amit Ruhela, Kento Sato, Koichi Shirahata, Tsuguchika Tabaru, Aristeidis Tsaris, Jan Balewski, Ben Cumming, Takumi Danjo, Jens Domke, Takaaki Fukai, Naoto Fukumoto, Tatsuya Fukushi, Balazs Gerofi, Takumi Honda, Toshiyuki Imamura, Akihiko Kasagi, Kentaro Kawakami, Shuhei Kudo, Akiyoshi Kuroda, Maxime Martinasso, Satoshi Matsuoka, Henrique Mendonça, Kazuki Minami, Prabhat Ram, Takashi Sawada, Mallikarjun Shankar, Tom St. John, Akihiro Tabuchi, Venkatram Vishwanath, Mohamed Wahib, Masafumi Yamazaki, Junqi Yin:
MLPerf™ HPC: A Holistic Benchmark Suite for Scientific Machine Learning on HPC Systems. MLHPC@SC 2021: 33-45 - 2016
- [c5]Takayuki Shibasaki, Takumi Danjo, Yuuki Ogata, Yasufumi Sakai, Hiroki Miyaoka, Futoshi Terasawa, Masahiro Kudo, Hideki Kano, Atsushi Matsuda, Shigeaki Kawai, Tomoyuki Arai, Hirohito Higashi, Naoaki Naka, Hisakatsu Yamaguchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura:
3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS. ISSCC 2016: 64-65 - [c4]Hiroki Miyaoka, Futoshi Terasawa, Masahiro Kudo, Hideki Kano, Atsushi Matsuda, Noriaki Shirai, Shigeaki Kawai, Takayuki Shibasaki, Takumi Danjo, Yuuki Ogata, Yasufumi Sakai, Hisakatsu Yamaguchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura, Yutaka Ide, Kazuhiro Terashima, Hirohito Higashi, Tomokazu Higuchi, Naoaki Naka:
A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS. VLSI Circuits 2016: 1-2 - 2014
- [c3]Kentaro Yoshioka, Ryo Saito, Takumi Danjo, Sanroku Tsukamoto, Hiroki Ishikuro:
7-bit 0.8-1.2GS/s Dynamic Architecture and Frequency Scaling subrange ADC with binary-search/flash Live Configuring Technique. VLSIC 2014: 1-2 - 2013
- [c2]Yoshiyasu Doi, Takayuki Shibasaki, Takumi Danjo, Win Chaivipas, Takushi Hashida, Hiroki Miyaoka, Masanori Hoshino, Yoichi Koyanagi, Takuji Yamamoto, Sanroku Tsukamoto, Hirotaka Tamura:
32Gb/s data-interpolator receiver with 2-tap DFE in 28nm CMOS. ISSCC 2013: 36-37 - 2012
- [c1]Takumi Danjo, Masato Yoshioka, Masayuki Isogai, Masanori Hoshino, Sanroku Tsukamoto:
A 6b, 1GS/s, 9.9mW interpolated subranging ADC in 65nm CMOS. VLSI-DAT 2012: 1-4
Informal and Other Publications
- 2021
- [i1]Steven Farrell, Murali Emani, Jacob Balma, Lukas Drescher, Aleksandr Drozd, Andreas Fink, Geoffrey C. Fox, David Kanter, Thorsten Kurth, Peter Mattson, Dawei Mu, Amit Ruhela, Kento Sato, Koichi Shirahata, Tsuguchika Tabaru, Aristeidis Tsaris, Jan Balewski, Ben Cumming, Takumi Danjo, Jens Domke, Takaaki Fukai, Naoto Fukumoto, Tatsuya Fukushi, Balazs Gerofi, Takumi Honda, Toshiyuki Imamura, Akihiko Kasagi, Kentaro Kawakami, Shuhei Kudo, Akiyoshi Kuroda, Maxime Martinasso, Satoshi Matsuoka, Henrique Mendonça, Kazuki Minami, Prabhat Ram, Takashi Sawada, Mallikarjun Shankar, Tom St. John, Akihiro Tabuchi, Venkatram Vishwanath, Mohamed Wahib, Masafumi Yamazaki, Junqi Yin:
MLPerf HPC: A Holistic Benchmark Suite for Scientific Machine Learning on HPC Systems. CoRR abs/2110.11466 (2021)
Coauthor Index
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