"A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase ..."

Hiroki Miyaoka et al. (2016)

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DOI: 10.1109/VLSIC.2016.7573472

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-21

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Hiroki Miyaoka, Futoshi Terasawa, Masahiro Kudo, Hideki Kano, Atsushi Matsuda, Noriaki Shirai, Shigeaki Kawai, Takayuki Shibasaki, Takumi Danjo, Yuuki Ogata, Yasufumi Sakai, Hisakatsu Yamaguchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura, Yutaka Ide, Kazuhiro Terashima, Hirohito Higashi, Tomokazu Higuchi, Naoaki Naka:
A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS. VLSI Circuits 2016: 1-2

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