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2010 – 2019
- 2012
[c8]Masato Uchiyama, Hideho Arakida, Yasuki Tanabe, Tsukasa Ike, Takanori Tamai, Moriyasu Banno:
Visconti2 - a heterogeneous multi-core SoC for image-recognition applications. Hot Chips Symposium 2012: 1-22- 2011
- [j6]Yu Kikuchi, Makoto Takahashi, Tomohisa Maeda, Masatoshi Fukuda, Yasuhiro Koshio, Hiroyuki Hara, Hideho Arakida, Hideaki Yamamoto, Yousuke Hagiwara, Tetsuya Fujita, Manabu Watanabe, Hirokazu Ezawa, Takayoshi Shimazawa, Yasuo Ohara, Takashi Miyamori, Mototsugu Hamada, Masafumi Takahashi, Yukihito Oowaki:
A 40 nm 222 mW H.264 Full-HD Decoding, 25 Power Domains, 14-Core Application Processor With x512b Stacked DRAM. IEEE J. Solid State Circuits 46(1): 32-41 (2011) - 2010
- [c7]Yu Kikuchi, Makoto Takahashi, Tomohisa Maeda, Hiroyuki Hara, Hideho Arakida, Hideaki Yamamoto, Yousuke Hagiwara, Tetsuya Fujita, Manabu Watanabe, Takayoshi Shimazawa, Yasuo Ohara, Takashi Miyamori, Mototsugu Hamada, Yukihito Oowaki:
A 222mW H.264 Full-HD decoding application processor with x512b stacked DRAM in 40nm. ISSCC 2010: 326-327
2000 – 2009
- 2009
- [j5]Tatsuya Mori, Yasuyuki Ueda, Nobuhiro Nonogaki, Toshihiro Terazawa, Milosz Sroka, Tetsuya Fujita, Takeshi Kodaka, Takayuki Mori, Kumiko Morita, Hideho Arakida, Takashi Miura, Yuji Okuda, Toshiki Kizu, Yoshiro Tsuboi:
A Power, Performance Scalable Eight-Cores Media Processor for Mobile Multimedia Applications. IEEE J. Solid State Circuits 44(11): 2957-2965 (2009) - [c6]Takeshi Kodaka, Shunsuke Sasaki, Takahiro Tokuyoshi, Ryuichiro Ohyama, Nobuhiro Nonogaki, Koji Kitayama, Tatsuya Mori, Yasuyuki Ueda, Hideho Arakida, Yuji Okuda, Toshiki Kizu, Yoshiro Tsuboi, Nobu Matsumoto:
Design and implementation of scalable, transparent threads for multi-core media processor. DATE 2009: 1035-1039 - 2008
- [j4]Jacob Leverich, Hideho Arakida, Alex Solomatnikov, Amin Firoozshahian, Mark Horowitz, Christos Kozyrakis:
Comparative evaluation of memory models for chip multiprocessors. ACM Trans. Archit. Code Optim. 5(3): 12:1-12:30 (2008) - 2007
- [c5]Jacob Leverich, Hideho Arakida, Alex Solomatnikov, Amin Firoozshahian, Mark Horowitz, Christos Kozyrakis:
Comparing memory systems for chip multiprocessors. ISCA 2007: 358-368 - 2006
- [j3]Toshihide Fujiyoshi, Shinichiro Shiratake, Shuou Nomura, Tsuyoshi Nishikawa, Yoshiyuki Kitasho, Hideho Arakida, Yuji Okuda, Yoshiro Tsuboi, Mototsugu Hamada, Hiroyuki Hara, Tetsuya Fujita, Fumitoshi Hatori, Takayoshi Shimazawa, Kunihiko Yahagi, Hideki Takeda, Masami Murakata, Fumihiro Minami, Naoyuki Kawabe, Takeshi Kitahara, Katsuhiro Seta, Masafumi Takahashi, Yukihito Oowaki, Tohru Furuyama:
A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling. IEEE J. Solid State Circuits 41(1): 54-62 (2006) - 2001
- [c4]Masafumi Takahashi, Tsuyoshi Nishikawa, Hideho Arakida, Tohru Furuyama:
A Single-Chip Low-Power Mpeg-4 Audiovisual Lsi Using Embedded Dram Technology. ICME 2001 - 2000
- [j2]Masafumi Takahashi, Tsuyoshi Nishikawa, Mototsugu Hamada, Toshinari Takayanagi, Hideho Arakida, Noriaki Machida, Hideaki Yamamoto, Toshihide Fujiyoshi, Yoko Ohashi, Osamu Yamagishi, Tatsuo Samata, Atsushi Asano, Toshihiro Terazawa, Kenji Ohmori, Yoshinori Watanabe, Hiroki Nakamura, Shigenobu Minami, Tadahiro Kuroda, Tohru Furuyama:
A 60-MHz 240-mW MPEG-4 videophone LSI with 16-Mb embedded DRAM. IEEE J. Solid State Circuits 35(11): 1713-1721 (2000) - [c3]Masafumi Takahashi, Tsuyoshi Nishikawa, Hideho Arakida, Noriaki Machida, Hideaki Yamamoto, Toshihide Fujiyoshi, Yoko Matsumoto, Osamu Yamagishi, Tatsuo Samata, Atsushi Asano, Toshihiro Terazawa, Kenji Ohmori, Junya Shirakura, Yoshinori Watanabe, Hiroki Nakamura, Shigenobu Minami, Tohru Furuyama:
A scalable MPEG-4 video codec architecture for IMT-2000 multimedia applications. ISCAS 2000: 188-191
1990 – 1999
- 1998
- [j1]Masafumi Takahashi, Mototsugu Hamada, Tsuyoshi Nishikawa, Hideho Arakida, Tetsuya Fujita, Fumitoshi Hatori, Shinji Mita, Kojiro Suzuki, Akihiko Chiba, Toshihiro Terazawa, Fumihiko Sano, Yoshinori Watanabe, Kimiyoshi Usami, Mutsunori Igarashi, Takashi Ishikawa, Masahiro Kanazawa, Tadahiro Kuroda, Tohru Furuyama:
A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme. IEEE J. Solid State Circuits 33(11): 1772-1780 (1998) - [c2]Mototsugu Hamada, Masafumi Takahashi, Hideho Arakida, Akihiko Chiba, Toshihiro Terazawa, Takashi Ishikawa, Masahiro Kanazawa, Mutsunori Igarashi, Kimiyoshi Usami, Tadahiro Kuroda:
A top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme. CICC 1998: 495-498 - [c1]Kimiyoshi Usami, Mutsunori Igarashi, Takashi Ishikawa, Masahiro Kanazawa, Masafumi Takahashi, Mototsugu Hamada, Hideho Arakida, Toshihiro Terazawa, Tadahiro Kuroda:
Design Methodology of Ultra Low-Power MPEG4 Codec Core Exploiting Voltage Scaling Techniques. DAC 1998: 483-488
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