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2020 – today
- 2023
[c7]Takumi Fujimori
, Shuou Nomura:
BOOSTER: Rethinking the erase operation of low-latency SSDs to achieve high throughput and less long latency. SYSTOR 2023: 94-104- 2021
- [j2]Tomoya Suzuki, Kazuhiro Hiwada, Hirotsugu Kajihara, Shintaro Sano, Shuou Nomura, Tatsuo Shiozawa:
Approaching DRAM performance by using microsecond-latency flash memory for small-sized random read accesses: a new access method and its graph applications. Proc. VLDB Endow. 14(8): 1311-1324 (2021)
2010 – 2019
- 2011
- [c6]Shuou Nomura, Matthew D. Sinclair, Chen-Han Ho, Venkatraman Govindaraju, Marc de Kruijf, Karthikeyan Sankaralingam:
Sampling + DMR: practical and low-overhead permanent fault detection. ISCA 2011: 201-212 - 2010
- [c5]Marc de Kruijf, Shuou Nomura, Karthikeyan Sankaralingam:
A unified model for timing speculation: Evaluating the impact of technology scaling, CMOS design style, and fault recovery mechanism. DSN 2010: 487-496 - [c4]Marc de Kruijf, Shuou Nomura, Karthikeyan Sankaralingam:
Relax: an architectural framework for software recovery of hardware faults. ISCA 2010: 497-508 - [c3]Shuou Nomura, Karthikeyan Sankaralingam, Ranganathan Sankaralingam:
A fast and highly accurate path delay emulation framework for logic-emulation of timing speculation. ITC 2010: 635-644
2000 – 2009
- 2008
- [c2]Fumihiko Tachibana, Hironori Sato, Takahiro Yamashita, Hiroyuki Hara, Takeshi Kitahara, Shuou Nomura, Fumiyuki Yamane, Yoshiro Tsuboi, Keiko Seki, Shuuji Matsumoto, Yoshinori Watanabe, Mototsugu Hamada:
A process variation compensation scheme using cell-based forward body-biasing circuits usable for 1.2V design. CICC 2008: 29-32 - [c1]Shuou Nomura, Fumihiko Tachibana, Tetsuya Fujita, Chen Kong Teh, Hiroyuki Usui, Fumiyuki Yamane, Yukimasa Miyamoto, Chaiyasit Kumtornkittikul, Hiroyuki Hara, Takahiro Yamashita, Jun Tanabe, Masaru Uchiyama, Yoshiro Tsuboi, Takashi Miyamori, Takeshi Kitahara, Hironori Sato, Y. Homma, Shuuji Matsumoto, Keiko Seki, Y. Watanabe, Mototsugu Hamada, Makoto Takahashi:
A 9.7mW AAC-Decoding, 620mW H.264 720p 60fps Decoding, 8-Core Media Processor with Embedded Forward-Body-Biasing and Power-Gating Circuit in 65nm CMOS Technology. ISSCC 2008: 262-263 - 2006
- [j1]Toshihide Fujiyoshi, Shinichiro Shiratake, Shuou Nomura, Tsuyoshi Nishikawa, Yoshiyuki Kitasho, Hideho Arakida, Yuji Okuda, Yoshiro Tsuboi, Mototsugu Hamada, Hiroyuki Hara, Tetsuya Fujita, Fumitoshi Hatori, Takayoshi Shimazawa, Kunihiko Yahagi, Hideki Takeda, Masami Murakata, Fumihiro Minami, Naoyuki Kawabe, Takeshi Kitahara, Katsuhiro Seta, Masafumi Takahashi, Yukihito Oowaki, Tohru Furuyama:
A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling. IEEE J. Solid State Circuits 41(1): 54-62 (2006)
Coauthor Index
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