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2020 – today
- 2024
[i2]Yu Nakanishi, Kazuhiro Hiwada, Yosuke Bando, Tomoya Suzuki, Hirotsugu Kajihara, Shintaro Sano, Tatsuro Endo, Tatsuo Shiozawa:
Implementing and Evaluating E2LSH on Storage. CoRR abs/2403.16404 (2024)- 2023
- [c4]Yu Nakanishi, Kazuhiro Hiwada, Yosuke Bando, Tomoya Suzuki, Hirotsugu Kajihara, Shintaro Sano, Tatsuro Endo, Tatsuo Shiozawa:
Implementing and Evaluating E2LSH on Storage. EDBT 2023: 437-449 - [c3]Shintaro Sano
, Yosuke Bando, Kazuhiro Hiwada, Hirotsugu Kajihara, Tomoya Suzuki, Yu Nakanishi, Daisuke Taki, Akiyuki Kaneko, Tatsuo Shiozawa:
GPU Graph Processing on CXL-Based Microsecond-Latency External Memory. SC Workshops 2023: 961-972 - [i1]Shintaro Sano, Yosuke Bando, Kazuhiro Hiwada, Hirotsugu Kajihara, Tomoya Suzuki, Yu Nakanishi, Daisuke Taki, Akiyuki Kaneko, Tatsuo Shiozawa:
GPU Graph Processing on CXL-Based Microsecond-Latency External Memory. CoRR abs/2312.03113 (2023) - 2021
- [j3]Tomoya Suzuki, Kazuhiro Hiwada, Hirotsugu Kajihara, Shintaro Sano, Shuou Nomura, Tatsuo Shiozawa:
Approaching DRAM performance by using microsecond-latency flash memory for small-sized random read accesses: a new access method and its graph applications. Proc. VLDB Endow. 14(8): 1311-1324 (2021)
2010 – 2019
- 2013
- [j2]Toshiyuki Yamagishi, Tatsuo Shiozawa, Koji Horisaki, Hiroyuki Hara, Yasuo Unekawa:
A Standard-Cell Based On-Chip NMOS and PMOS Performance Monitor for Process Variability Compensation. IEICE Trans. Electron. 96-C(6): 894-902 (2013) - 2012
- [c2]Toshiyuki Yamagishi, Tatsuo Shiozawa, Koji Horisaki, Hiroyuki Hara, Yasuo Unekawa:
An area-efficient, standard-cell based on-chip NMOS and PMOS performance monitor for process variability compensation. COOL Chips 2012: 1-3 - 2011
- [c1]Daisuke Taki, Tatsuo Shiozawa, Kuniaki Ito, Youichiro Shiba, Kouji Horisaki, Hirotsugu Kajihara, Toshiyuki Yamagishi, Masahiro Sekiya, Akira Yamaga, Tetsuya Fujita, Hiroyuki Hara, Masanori Kuwahara, Toshio Fujisawa, Yasuo Unekawa:
A 7uW deep-sleep, ultra low-power WLAN baseband LSI for mobile applications. COOL Chips 2011: 1-3
2000 – 2009
- 2003
- [j1]Toshio Fujisawa, Jun Hasegawa, Koji Tsuchie, Tatsuo Shiozawa, Tetsuya Fujita, Toshitada Saito, Yasuo Unekawa:
A single-chip 802.11a MAC/PHY with a 32-b RISC processor. IEEE J. Solid State Circuits 38(11): 2001-2009 (2003)
Coauthor Index
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