"An area-efficient, standard-cell based on-chip NMOS and PMOS performance ..."

Toshiyuki Yamagishi et al. (2012)

> Home

Details and statistics

DOI: 10.1109/COOLCHIPS.2012.6216586

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

- view
  authority control:
- export record
  dblp key:
  - conf/coolchips/YamagishiSHHU12
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/coolchips/YamagishiSHHU12
Toshiyuki Yamagishi, Tatsuo Shiozawa, Koji Horisaki, Hiroyuki Hara, Yasuo Unekawa:
An area-efficient, standard-cell based on-chip NMOS and PMOS performance monitor for process variability compensation. COOL Chips 2012: 1-3

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.