"A 0.5 V 1.1 MS/sec 6.3 fJ/Conversion-Step SAR-ADC With Tri-Level ..."

Akira Shikata et al. (2012)

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DOI: 10.1109/JSSC.2012.2185352

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type: Journal Article

metadata version: 2020-08-30

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Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro:
A 0.5 V 1.1 MS/sec 6.3 fJ/Conversion-Step SAR-ADC With Tri-Level Comparator in 40 nm CMOS. IEEE J. Solid State Circuits 47(4): 1022-1030 (2012)

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