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2010 – 2019
- 2010
[j5]Yoichi Yoshida, Koichi Nose, Yoshihiro Nakagawa, Koichiro Noguchi, Yasuhiro Morita, Masamoto Tago, Masayuki Mizuno, Tadahiro Kuroda:
An Inductive-Coupling DC Voltage Transceiver for Highly Parallel Wafer-Level Testing. IEEE J. Solid State Circuits 45(10): 2057-2065 (2010)
2000 – 2009
- 2009
- [j4]Yoichiro Kurita, Koji Soejima, Katsumi Kikuchi, Masatake Takahashi, Masamoto Tago, Masahiro Koike, Koujirou Shibuya, Shintaro Yamamichi, Masaya Kawano:
A 3-D Packaging Technology with Highly-Parallel Memory/Logic Interconnect. IEICE Trans. Electron. 92-C(12): 1512-1522 (2009) - [c2]Yoichi Yoshida, Koichi Nose, Yoshihiro Nakagawa, Koichiro Noguchi, Yasuhiro Morita, Masamoto Tago, Tadahiro Kuroda, Masayuki Mizuno:
Wireless DC voltage transmission using inductive-coupling channelfor highly-parallel wafer-level testing. ISSCC 2009: 470-471 - 2007
- [j3]Kiichi Niitsu
, Noriyuki Miura, Mari Inoue, Yoshihiro Nakagawa, Masamoto Tago, Masayuki Mizuno, Takayasu Sakurai, Tadahiro Kuroda:
Daisy Chain Transmitter for Power Reduction in Inductive-Coupling CMOS Link. IEICE Trans. Electron. 90-C(4): 829-835 (2007) - [j2]Noriyuki Miura, Daisuke Mizoguchi, Mari Inoue, Kiichi Niitsu, Yoshihiro Nakagawa, Masamoto Tago, Muneo Fukaishi, Takayasu Sakurai, Tadahiro Kuroda:
A 1 Tb/s 3 W Inductive-Coupling Transceiver for 3D-Stacked Inter-Chip Clock and Data Link. IEEE J. Solid State Circuits 42(1): 111-122 (2007) - 2006
- [c1]Noriyuki Miura, Daisuke Mizoguchi, Mari Inoue, Kiichi Niitsu, Yoshihiro Nakagawa, Masamoto Tago, Muneo Fukaishi, Takayasu Sakurai, Tadahiro Kuroda:
A 1Tb/s 3W inductive-coupling transceiver for inter-chip clock and data link. ISSCC 2006: 1676-1685 - 2003
- [j1]Kenji Takahashi, Mitsuo Umemoto, Naotaka Tanaka, Kazumasa Tanida, Yoshihiko Nemoto, Yoshihiro Tomita, Masamoto Tago, Manabu Bonkohara:
Ultra-high-density interconnection technology of three-dimensional packaging. Microelectron. Reliab. 43(8): 1267-1279 (2003)
Coauthor Index
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