"A 3-D Packaging Technology with Highly-Parallel Memory/Logic Interconnect."

Yoichiro Kurita et al. (2009)

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DOI: 10.1587/TRANSELE.E92.C.1512

access: closed

type: Journal Article

metadata version: 2020-04-11

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Yoichiro Kurita, Koji Soejima, Katsumi Kikuchi, Masatake Takahashi, Masamoto Tago, Masahiro Koike, Koujirou Shibuya, Shintaro Yamamichi, Masaya Kawano:
A 3-D Packaging Technology with Highly-Parallel Memory/Logic Interconnect. IEICE Trans. Electron. 92-C(12): 1512-1522 (2009)

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