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ORCIDIPSJ Transactions on System LSI Design Methodology, Volume 17
Volume 17, 2024
- Tohru Ishihara:
Message from the Editor-in-Chief. 1 - Tadahiro Kuroda:
Slashing IC Power and Democratizing IC Access for the Digital Age. 2-6 - Ryotaro Ohara, Atsushi Fukunaga, Masakazu Taichi, Masaya Kabuto, Riku Hamabe, Masato Ikegawa, Shintaro Izumi, Hiroshi Kawaguchi:
A Case Study for Improving Performances of Deep-Learning Processor with MRAM. 7-15 - Shota Nakabeppu, Nobuyuki Yamasaki:
A Learning-based Control Scheme for MTJ-based Non-volatile Flip-Flops. 16-35 - Takehiro Kitamura, Takashi Hisakado, Osami Wada, Mahfuzul Islam:
Design of Reference-free Flash ADC With On-chip Rank-based Comparator Selection Using Multiple Comparator Groups. 36-43 - Yuncheng Zhang, Kenichi Okada:
Design of Synthesizable Digital Phase Locked Loops. 44-54 - Hansen Wang, Dongju Li, Tsuyoshi Isshiki:
A Low-Power Reconfigurable DNN Accelerator for Instruction-Extended RISC-V. 55-66 - Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi, Mathieu Molongo, Makoto Minami, Katsuya Nishioka:
Two-layer Bottleneck Channel Track Assignment for Analog VLSI. 67-76 - Kensuke Iizuka, Kohei Ito, Ryota Yasudo, Hideharu Amano:
Power Optimized Design Framework for FPGA Clusters. 77-86
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