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2020 – today
- 2024
[c70]Ninnart Fuengfusin, Hakaru Tamukoh, Osamu Nomura, Takashi Morie:
Robust Binary Encoding for Ternary Neural Networks Toward Deployment on Emerging Memory. IJCNN 2024: 1-8- [c69]Akinobu Mizutani, Yuichiro Tanaka, Hakaru Tamukoh, Osamu Nomura, Katsumi Tateno, Takashi Morie:
A Hippocampus-Inspired Environment-Specific Knowledge Acquisition System Utilizing Common Knowledge with Contextual Information. IJCNN 2024: 1-8 - [c68]Yuka Shishido, Osamu Nomura, Katsumi Tateno, Hakaru Tamukoh, Takashi Morie:
CMOS digital-analog mixed signal VLSI implementation of a hippocampus-inspired model. IJCNN 2024: 1-8 - [c67]Soshi Hirayae, Kanta Yoshioka, Atsuki Yokota, Ichiro Kawashima, Yuichiro Tanaka, Yuichi Katori, Osamu Nomura, Takashi Morie, Hakaru Tamukoh:
Enhancing Memory Capacity of Reservoir Computing with Delayed Input and Efficient Hardware Implementation with Shift Registers. ISCAS 2024: 1-5 - [i15]Kosei Isomoto, Akinobu Mizutani, Fumiya Matsuzaki, Hikaru Sato, Ikuya Matsumoto, Kosei Yamao, Takuya Kawabata, Tomoya Shiba, Yuga Yano, Atsuki Yokota, Daiju Kanaoka, Hiromasa Yamaguchi, Kazuya Murai, Kim Minje, Lu Shen, Mayo Suzuka, Moeno Anraku, Naoki Yamaguchi, Satsuki Fujimatsu, Shoshi Tokuno, Tadataka Mizo, Tomoaki Fujino, Yuuki Nakadera, Yuka Shishido, Yusuke Nakaoka, Yuichiro Tanaka, Takashi Morie, Hakaru Tamukoh:
Hibikino-Musashi@Home 2024 Team Description Paper. CoRR abs/2410.06192 (2024) - [i14]Yusuke Sakemi, Yuji Okamoto, Takashi Morie, Sou Nobukawa, Takeo Hosomi, Kazuyuki Aihara:
Training Physical Neural Networks for Analog In-Memory Computing. CoRR abs/2412.09010 (2024) - 2023
- [j41]Yusuke Sakemi
, Kai Morino, Takashi Morie, Kazuyuki Aihara:
A Supervised Learning Algorithm for Multilayer Spiking Neural Networks Based on Temporal Coding Toward Energy-Efficient VLSI Processor Design. IEEE Trans. Neural Networks Learn. Syst. 34(1): 394-408 (2023) - [c66]Ninnart Fuengfusin, Hakaru Tamukoh, Yuichiro Tanaka, Osamu Nomura, Takashi Morie:
Efficient Repetition Coding for Deep Learning Towards Implementation Using Emerging Non-Volatile Memory with Write-Errors. IJCNN 2023: 1-6 - [c65]Kanta Yoshioka, Yuichi Katori, Yuichiro Tanaka, Osamu Nomura, Takashi Morie, Hakaru Tamukoh:
FPGA Implementation of a Chaotic Boltzmann Machine Annealer. IJCNN 2023: 1-8 - [i13]Yusuke Sakemi, Sou Nobukawa, Toshitaka Matsuki, Takashi Morie, Kazuyuki Aihara:
Learning Reservoir Dynamics with Temporal Self-Modulation. CoRR abs/2301.09235 (2023) - [i12]Tomoya Shiba, Akinobu Mizutani, Yuga Yano, Tomohiro Ono, Shoshi Tokuno, Daiju Kanaoka, Yukiya Fukuda, Hayato Amano, Mayu Koresawa, Yoshifumi Sakai, Ryogo Takemoto, Katsunori Tamai, Kazuo Nakahara, Hiroyuki Hayashi, Satsuki Fujimatsu, Yusuke Mizoguchi, Moeno Anraku, Mayo Suzuka, Lu Shen, Kohei Maeda, Fumiya Matsuzaki, Ikuya Matsumoto, Kazuya Murai, Kosei Isomoto, Kim Minje, Yuichiro Tanaka, Takashi Morie, Hakaru Tamukoh:
Hibikino-Musashi@Home 2023 Team Description Paper. CoRR abs/2310.12650 (2023) - 2022
- [j40]Hiroki Nakagawa, Katsumi Tateno, Kensuke Takada, Takashi Morie:
A Neural Network Model of the Entorhinal Cortex and Hippocampus for Event-Order Memory Processing. IEEE Access 10: 43003-43012 (2022) - [j39]Osamu Nomura, Yusuke Sakemi, Takeo Hosomi, Takashi Morie:
Robustness of Spiking Neural Networks Based on Time-to-First-Spike Encoding Against Adversarial Attacks. IEEE Trans. Circuits Syst. II Express Briefs 69(9): 3640-3644 (2022) - [c64]Ichiro Kawashima, Katsumi Tateno, Takashi Morie, Hakaru Tamukoh:
A memory-based entorhinal-hippocampal model and its FPGA implementation by on-chip RAMs. ISCAS 2022: 491-495 - [c63]Yusuke Sakemi, Kai Morino, Takashi Morie, Takeo Hosomi, Kazuyuki Aihara:
A Spiking Neural Network with Resistively Coupled Synapses Using Time-to-First-Spike Coding Towards Efficient Charge-Domain Computing. ISCAS 2022: 2152-2156 - [i11]Yutaro Ishida, Sansei Hori, Yuichiro Tanaka, Yuma Yoshimoto, Kouhei Hashimoto, Gouki Iwamoto, Yoshiya Aratani, Kenya Yamashita, Shinya Ishimoto, Kyosuke Hitaka, Fumiaki Yamaguchi, Ryuhei Miyoshi, Kentaro Honda, Yushi Abe, Yoshitaka Kato, Takashi Morie, Hakaru Tamukoh:
Hibikino-Musashi@Home 2018 Team Description Paper. CoRR abs/2211.04972 (2022) - [i10]Tomoya Shiba, Tomohiro Ono, Shoshi Tokuno, Issei Uchino, Masaya Okamoto, Daiju Kanaoka, Kazutaka Takahashi, Kenta Tsukamoto, Yoshiaki Tsutsumi, Yugo Nakamura, Yukiya Fukuda, Yusuke Hoji, Hayato Amano, Yuma Kubota, Mayu Koresawa, Yoshifumi Sakai, Ryogo Takemoto, Katsunori Tamai, Kazuo Nakahara, Hiroyuki Hayashi, Satsuki Fujimatsu, Akinobu Mizutani, Yusuke Mizoguchi, Yuhei Yoshimitsu, Mayo Suzuka, Ikuya Matsumoto, Yuga Yano, Yuichiro Tanaka, Takashi Morie, Hakaru Tamukoh:
Hibikino-Musashi@Home 2022 Team Description Paper. CoRR abs/2211.06696 (2022) - 2021
- [j38]Masatoshi Yamaguchi, Goki Iwamoto, Yuta Nishimura, Hakaru Tamukoh, Takashi Morie:
An Energy-Efficient Time-Domain Analog CMOS BinaryConnect Neural Network Processor Based on a Pulse-Width Modulation Approach. IEEE Access 9: 2644-2654 (2021) - [j37]Yoeng Jye Yeoh, Takashi Morie, Hakaru Tamukoh:
An efficient hardware-oriented dropout algorithm. Neurocomputing 427: 191-200 (2021) - [c62]Ichiro Kawashima, Yuichi Katori, Takashi Morie, Hakaru Tamukoh:
An area-efficient multiply-accumulation architecture and implementations for time-domain neural processing. FPT 2021: 1-4 - [c61]Akinobu Mizutani, Yuichiro Tanaka, Hakaru Tamukoh, Yuichi Katori, Katsumi Tateno, Takashi Morie:
Brain-inspired neural network navigation system with hippocampus, prefrontal cortex, and amygdala functions. ISPACS 2021: 1-2 - [i9]Yusuke Sakemi, Takashi Morie, Takeo Hosomi, Kazuyuki Aihara:
Effects of VLSI Circuit Constraints on Temporal-Coding Multilayer Spiking Neural Networks. CoRR abs/2106.10382 (2021) - 2020
- [j36]Ichiro Kawashima, Takashi Morie, Hakaru Tamukoh:
FPGA Implementation of Hardware-Oriented Chaotic Boltzmann Machines. IEEE Access 8: 204360-204377 (2020) - [j35]Yuichiro Tanaka, Takashi Morie, Hakaru Tamukoh:
An Amygdala-Inspired Classical Conditioning Model Implemented on an FPGA for Home Service Robots. IEEE Access 8: 212066-212078 (2020) - [j34]Yutaro Ishida, Takashi Morie, Hakaru Tamukoh:
A hardware intelligent processing accelerator for domestic service robots. Adv. Robotics 34(14): 947-957 (2020) - [i8]Yusuke Sakemi, Kai Morino, Takashi Morie, Kazuyuki Aihara:
A Supervised Learning Algorithm for Multilayer Spiking Neural Networks Based on Temporal Coding Toward Energy-Efficient VLSI Processor Design. CoRR abs/2001.05348 (2020) - [i7]Tomohiro Ono, Yuichiro Tanaka, Yutaro Ishida, Yushi Abe, Kazuki Kanamaru, Daichi Kamimura, Kentaro Nakamura, Yuta Nishimura, Shoshi Tokuno, Yuya Mii, Morio Yamauchi, Yuichiro Uemura, Takunori Hashimoto, Yugo Nakamura, Issei Uchino, Daiju Kanaoka, Takeru Hanyu, Kenta Tsukamoto, Takashi Morie, Hakaru Tamukoh:
Hibikino-Musashi@Home 2020 Team Description Paper. CoRR abs/2005.14451 (2020) - [i6]Yuichiro Tanaka, Yutaro Ishida, Yushi Abe, Tomohiro Ono, Kohei Kabashima, Takuma Sakata, Masashi Fukuyado, Fuyuki Muto, Takumi Yoshii, Kazuki Kanamaru, Daichi Kamimura, Kentaro Nakamura, Yuta Nishimura, Takashi Morie, Hakaru Tamukoh:
Hibikino-Musashi@Home 2019 Team Description Paper. CoRR abs/2006.01233 (2020)
2010 – 2019
- 2019
- [c60]Yuichi Katori, Hakaru Tamukoh, Takashi Morie:
Reservoir Computing Based on Dynamics of Pseudo-Billiard System in Hypercube. IJCNN 2019: 1-8 - [c59]Masatoshi Yamaguchi, Yuichi Katori, Daichi Kamimura, Hakaru Tamukoh, Takashi Morie:
A Chaotic Boltzmann Machine Working as a Reservoir and Its Analog VLSI Implementation. IJCNN 2019: 1-7 - [c58]Masatoshi Yamaguchi, Gouki Iwamoto, Yushi Abe, Yuichiro Tanaka, Yutaro Ishida, Hakaru Tamukoh, Takashi Morie:
Live Demonstration: A VLSI Implementation of Time-Domain Analog Weighted-Sum Calculation Model for Intelligent Processing on Robots. ISCAS 2019: 1 - [i5]Masatoshi Yamaguchi, Goki Iwamoto, Hakaru Tamukoh, Takashi Morie:
An Energy-efficient Time-domain Analog VLSI Neural Network Processor Based on a Pulse-width Modulation Approach. CoRR abs/1902.07707 (2019) - [i4]Yoeng Jye Yeoh, Takashi Morie, Hakaru Tamukoh:
An Efficient Hardware-Oriented Dropout Algorithm. CoRR abs/1911.05941 (2019) - 2018
- [c57]Yutaro Ishida, Takashi Morie, Hakaru Tamukoh:
Live Demonstration: A Hardware Accelerated Robot Middleware Package for Intelligent Processing on Robots. ISCAS 2018: 1- - [c56]Yutaro Ishida, Takashi Morie, Hakaru Tamukoh:
A Hardware Accelerated Robot Middleware Package for Intelligent Processing on Robots. ISCAS 2018: 1-5 - [i3]Quan Wang, Hakaru Tamukoh, Takashi Morie:
A Time-domain Analog Weighted-sum Calculation Model for Extremely Low Power VLSI Implementation of Multi-layer Neural Networks. CoRR abs/1810.06819 (2018) - 2017
- [j33]Dinda Pramanta, Takashi Morie, Hakaru Tamukoh:
Synchronization of Pulse-Coupled Phase Oscillators over Multi-FPGA Communication Links. J. Robotics Netw. Artif. Life 4(1): 91-96 (2017) - [c55]Yoeng Jye Yeoh, Takashi Morie, Hakaru Tamukoh:
A Hardware-Oriented Dropout Algorithm for Efficient FPGA Implementation. ICONIP (6) 2017: 821-829 - [c54]Masatoshi Yamaguchi, Hakaru Tamukoh, Hideyuki Suzuki, Takashi Morie:
A CMOS chaotic Boltzmann machine circuit and three-neuron network operation. IJCNN 2017: 1218-1224 - [i2]Sansei Hori, Yutaro Ishida, Yuta Kiyama, Yuichiro Tanaka, Yuki Kuroda, Masataka Hisano, Yuto Imamura, Tomotaka Himaki, Yuma Yoshimoto, Yoshiya Aratani, Kouhei Hashimoto, Gouki Iwamoto, Hiroto Fujita, Takashi Morie, Hakaru Tamukoh:
Hibikino-Musashi@Home 2017 Team Description Paper. CoRR abs/1711.05457 (2017) - 2016
- [c53]Sansei Hori, Takashi Morie, Hakaru Tamukoh:
Restricted Boltzmann Machines Without Random Number Generators for Efficient Digital Hardware Implementation. ICANN (1) 2016: 391-398 - [c52]Akihiro Suzuki, Takashi Morie, Hakaru Tamukoh:
FPGA Implementation of Autoencoders Having Shared Synapse Architecture. ICONIP (1) 2016: 231-239 - [c51]Quan Wang, Hakaru Tamukoh, Takashi Morie:
Time-Domain Weighted-Sum Calculation for Ultimately Low Power VLSI Neural Networks. ICONIP (1) 2016: 240-247 - [c50]Masatoshi Yamaguchi, Takashi Kato, Quan Wang, Hideyuki Suzuki, Hakaru Tamukoh, Takashi Morie:
A CMOS Unit Circuit Using Subthreshold Operation of MOSFETs for Chaotic Boltzmann Machines. ICONIP (1) 2016: 248-255 - [c49]Ludovic Hofer, Michio Tanaka, Hakaru Tamukoh, Amir Ali Forough Nassiraei, Takashi Morie:
Depth-Based Visual Servoing Using Low-Accurate Arm. SCIS&ISIS 2016: 524-531 - [i1]Ludovic Hofer, Michio Tanaka, Hakaru Tamukoh, Amir Ali Forough Nassiraei, Takashi Morie:
Depth-Based Visual Servoing Using Low-Accurate Arm. CoRR abs/1612.03784 (2016) - 2015
- [j32]Youngjae Kim, Takashi Morie:
A PWM-Mode Pixel-Parallel Image-Processing Circuit Performing Directional State-Propagation and Its Application to Subjective Contour Generation. Circuits Syst. Signal Process. 34(2): 605-623 (2015) - [j31]Yasuhiro Suedomi, Hakaru Tamukoh, Kenji Matsuzaka, Michio Tanaka, Takashi Morie:
Parameterized digital hardware design of pulse-coupled phase oscillator networks. Neurocomputing 165: 54-62 (2015) - [j30]Michio Tanaka, Hiroki Matsubara, Takashi Morie:
Human Detection and Face Recognition Using 3D Structure of Head and Face Surfaces Detected by RGB-D Sensor. J. Robotics Mechatronics 27(6): 691-697 (2015) - [j29]Takuji Miki, Takashi Morie, Kazuo Matsukawa, Yoji Bando, Takeshi Okumoto, Koji Obata, Shiro Sakiyama, Shiro Dosho:
A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques. IEEE J. Solid State Circuits 50(6): 1372-1381 (2015) - [c48]Hiroki Sou, Takashi Morie:
A pixel-parallel state-propagation algorithm with self-update of propagation direction for subjective contour generation. ISPACS 2015: 53-56 - 2014
- [j28]Haichao Liang, Takashi Morie:
A motion detection model inspired by hippocampal function and its applications to obstacle detection. Neurocomputing 129: 59-66 (2014) - [j27]Shaohua Qian, Joo Kooi Tan, Hyoungseop Kim, Seiji Ishikawa, Takashi Morie, Takashi Shinomiya:
Comparing Effectiveness of Feature Detectors in Obstacles Detection from a Video. J. Robotics Netw. Artif. Life 1(3): 184-188 (2014) - [c47]Takashi Morie, Haichao Liang, Yilai Sun, Takashi Tohara, Makoto Igarashi, Seiji Samukawa:
A silicon nanodisk array structure realizing synaptic response of spiking neuron models with noise. ASP-DAC 2014: 185-190 - [c46]Hakaru Tamukoh, Kensuke Koga, Hideaki Harada, Takashi Morie:
Morphological Associative Memory Employing a Split Store Method. ICONIP (3) 2014: 341-348 - [c45]Takayuki Abe, Takashi Morie, Kazutoshi Satou, Daisuke Nomasaki, Shigeki Nakamura, Yoichiro Horiuchi, Koji Imamura:
An ultra-low-power 2-step wake-up receiver for IEEE 802.15.4g wireless sensor networks. VLSIC 2014: 1-2 - 2013
- [c44]Yasuhiro Suedomi, Hakaru Tamukoh, Michio Tanaka, Kenji Matsuzaka, Takashi Morie:
Parameterized Digital Hardware Design of Pulse-Coupled Phase Oscillator Model toward Spike-Based Computing. ICONIP (3) 2013: 17-24 - [c43]Takashi Morie, Takuji Miki, Kazuo Matsukawa, Yoji Bando, Takeshi Okumoto, Koji Obata, Shiro Sakiyama, Shiro Dosho:
A 71dB-SNDR 50MS/s 4.2mW CMOS SAR ADC by SNR enhancement techniques utilizing noise. ISSCC 2013: 272-273 - 2012
- [j26]Haichao Liang, Takashi Morie:
A Motion Detection Model Inspired by the Neuronal Propagation in the Hippocampus. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(2): 576-585 (2012) - [j25]Yasuto Arakaki, Hayaru Shouno, Kazuyuki Takahashi, Takashi Morie:
A Hierarchical Extension of the HOG Model Implemented in the Convolution-net for Human Detection. Inf. Media Technol. 7(4): 1480-1488 (2012) - [j24]Takuji Miki, Takashi Morie, Toshiaki Ozeki, Shiro Dosho:
An 11-b 300-MS/s Double-Sampling Pipelined ADC With On-Chip Digital Calibration for Memory Effects. IEEE J. Solid State Circuits 47(11): 2773-2782 (2012) - [c42]Shaohua Qian, Joo Kooi Tan, Hyoungseop Kim, Seiji Ishikawa, Takashi Morie:
Obstacles Extraction Using a Moving Camera. ACCV Workshops (2) 2012: 441-453 - [c41]Shaohua Qian, Joo Kooi Tan, Hyoungseop Kim, Seiji Ishikawa, Takashi Morie:
Obstacles Extraction from a Video Taken by a Moving Camera. ICCVE 2012: 268-273 - 2011
- [c40]Takashi Morie, Daisuke Atuti, Kazuki Ifuku, Yoshihiko Horio, Kazuyuki Aihara:
A CMOS nonlinear-map circuit array for threshold-coupled chaotic maps using pulse-modulation approach. ECCTD 2011: 126-129 - [c39]Frank L. Maldonado Huayaney, Hideki Tanaka, Takayuki Matsuo, Takashi Morie, Kazuyuki Aihara:
A VLSI Spiking Neural Network with Symmetric STDP and Associative Memory Operation. ICONIP (3) 2011: 381-388 - [c38]Haichao Liang, Takashi Morie:
A Motion Detection Model Inspired by Hippocampal Function and Its FPGA Implementation. ICONIP (3) 2011: 522-529 - [c37]Kenji Matsuzaka, Kazuki Nakada, Takashi Morie:
Analog CMOS circuit implementation of a system of pulse-coupled oscillators for spike-based computation. ISCAS 2011: 2849-2852 - 2010
- [j23]Kazuki Nakada, Kenji Matsuzaka, Takashi Morie:
Coarse Image Region Segmentation in Spatio-Temporal Domain Using a Region-based Coupled MRF Model with Phase Dynamics. Aust. J. Intell. Inf. Process. Syst. 11(2) (2010) - [j22]Yuuki Nakashima, Joo Kooi Tan, Seiji Ishikawa, Takashi Morie:
On detecting a human and its body direction from a video. Artif. Life Robotics 15(4): 455-458 (2010) - [j21]Joo Kooi Tan, Kazuki Inumaru, Seiji Ishikawa, Takashi Morie:
Automatic detection of pedestrians from stereo camera images. Artif. Life Robotics 15(4): 459-463 (2010) - [c36]Haichao Liang, Kazuki Nakada, Kenji Matsuzaka, Takashi Morie, Masato Okada:
Parametric Control in a Region-Based Coupled MRF Model with Phase Dynamics for Coarse Image Region Segmentation. CSE 2010: 190-195 - [c35]Takashi Morie, Yilai Sun, Haichao Liang, Makoto Igarashi, Chi-Hsien Huang, Seiji Samukawa:
A 2-dimensional Si nanodisk array structure for spiking neuron models. ISCAS 2010: 781-784 - [c34]Haichao Liang, Takashi Morie:
Coarse Image Edge Detection using Self-adjusting Resistive-fuse Networks. PRIS 2010: 43-52 - [p3]Ishtiaq Rasool Khan, Takashi Morie, Hiroyuki Miyamoto, Yasutaka Kuriya, Masaki Shimizu:
Real-Time Human-Machine Interaction System Based on Face Authentication and Arm Posture Recognition. Brain-Inspired Information Technology 2010: 141-145 - [p2]Takuji Kamada, Akitoshi Hanazawa, Takashi Morie:
Shadow Elimination Mimicking the Human Visual System. Brain-Inspired Information Technology 2010: 147-151 - [p1]Haichao Liang, Youhei Suzuki, Takashi Morie, Kazuki Nakada, Tsutomu Miki, Hatsuo Hayashi:
An FPGA-Based Collision Warning System Using Moving-Object Detection Inspired by Neuronal Propagation in the Hippocampus. Brain-Inspired Information Technology 2010: 153-158
2000 – 2009
- 2009
- [j20]Daisuke Atuti, Takashi Morie, Kazuyuki Aihara:
A Current-Sampling-Mode CMOS Arbitrary Chaos Generator Circuit Using Pulse Modulation Approach. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(5): 1308-1315 (2009) - [j19]Hideki Tanaka, Takashi Morie, Kazuyuki Aihara:
A CMOS Spiking Neural Network Circuit with Symmetric/Asymmetric STDP Function. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(7): 1690-1698 (2009) - [j18]Takashi Morie:
Single-Electron Devices and Circuits Utilizing Stochastic Operation for Intelligent Information Processing. Int. J. Nanotechnol. Mol. Comput. 1(2): 1-28 (2009) - [j17]Tsuyoshi Ebuchi, Yoshihide Komatsu, Tatsuo Okamoto, Yukio Arima, Yuji Yamada, Kazuaki Sogawa, Kouji Okamoto, Takashi Morie, Takashi Hirata, Shiro Dosho, Takefumi Yoshikawa:
A 125-1250 MHz Process-Independent Adaptive Bandwidth Spread Spectrum Clock Generator With Digital Controlled Self-Calibration. IEEE J. Solid State Circuits 44(3): 763-774 (2009) - [c33]Kazuo Matsukawa, Takashi Morie, Yusuke Tokunaga, Shiro Sakiyama, Yosuke Mitani, Masao Takayama, Takuji Miki, Akinori Matsumoto, Koji Obata, Shiro Dosho:
Design methods for pipeline & delta-sigma A-to-D converters with convex optimization. ASP-DAC 2009: 690-695 - [c32]Yusuke Kawashima, Daisuke Atuti, Kazuki Nakada, Masato Okada, Takashi Morie:
Coarse image region segmentation using region-and boundary-based coupled MRF models and their PWM VLSI implementation. IJCNN 2009: 1559-1565 - [c31]Takashi Morie, Youngjae Kim:
A subjective-contour generation LSI system with expandable pixel-parallel architecture for vision systems. ISSCC 2009: 478-479 - [c30]Ken Okamoto, Toshio Watanabe, Akitoshi Hanazawa, Takashi Morie, Hiroshi Ban, Yuji Maeda:
Video Monitoring of Slope Failure Using Spatiotemporal Gabor Filtering. SMC 2009: 960-965 - 2008
- [j16]Akinori Matsumoto, Shiro Sakiyama, Yusuke Tokunaga, Takashi Morie, Shiro Dosho:
A Design Method and Developments of a Low-Power and High-Resolution Multiphase Generation System. IEEE J. Solid State Circuits 43(4): 831-843 (2008) - [c29]Daisuke Atuti, Kazuki Nakada, Takashi Morie:
CMOS pulse-modulation circuit implementation of phase-locked loop neural networks. ISCAS 2008: 2174-2177 - [c28]Ishtiaq Rasool Khan, Hiroyuki Miyamoto, Takashi Morie:
Face and arm-posture recognition for secure human-machine interaction. SMC 2008: 411-417 - 2007
- [j15]Shiro Dosho, Naoshi Yanagisawa, Kazuaki Sogawa, Yuji Yamada, Takashi Morie:
An Ultra-Wide Range Digitally Adaptive Control Phase Locked Loop with New 3-Phase Switched Capacitor Loop Filter. IEICE Trans. Electron. 90-C(6): 1197-1202 (2007) - [c27]Daisuke Atuti, Naoto Kato, Kazuki Nakada, Takashi Morie:
CMOS circuit implementation of a coupled phase oscillator system using pulse modulation approach. ECCTD 2007: 827-830 - [c26]Haichao Liang, Takashi Morie, Youhei Suzuki, Kazuki Nakada, Tsutomu Miki, Hatsuo Hayashi:
An FPGA-based CollisionWarning System Using Hybrid Approach. HIS 2007: 30-35 - [c25]Osamu Nomura, Takashi Morie:
Projection-Field-Type VLSI Convolutional Neural Networks Using Merged/Mixed Analog-Digital Approach. ICONIP (1) 2007: 1081-1090 - 2006
- [j14]Teppei Nakano, Takashi Morie, Hideaki Ishizu, Hiroshi Ando, Atsushi Iwata:
FPGA Implementation of Resistive-Fuse Networks for Coarse Image-Region Segmentation. Intell. Autom. Soft Comput. 12(3): 307-316 (2006) - [j13]Shiro Dosho, Takashi Morie, Koji Okamoto, Yuji Yamada, Kazuaki Sogawa:
A -90 dBc@ 10 kHz Phase Noise Fractional-N Frequency Synthesizer with Accurate Loop Bandwidth Control Circuit. IEICE Trans. Electron. 89-C(6): 739-745 (2006) - [j12]Osamu Nomura, Takashi Morie, Keisuke Korekado, Teppei Nakano, Masakazu Matsugu, Atsushi Iwata:
An Image-Filtering LSI Processor Architecture for Face/Object Recognition Using a Sorted Projection-Field Model Based on a Merged/Mixed Analog-Digital Architecture. IEICE Trans. Electron. 89-C(6): 781-791 (2006) - [j11]Kan'ya Sasaki, Takashi Morie, Atsushi Iwata:
A VLSI Spiking Feedback Neural Network with Negative Thresholding and Its Application to Associative Memory. IEICE Trans. Electron. 89-C(11): 1637-1644 (2006) - [c24]Daisuke Atuti, Takashi Morie, Kazuyuki Aihara:
A Current-Sampling-Mode Arbitrary Chaos Generator Circuit Using Pulse Modulation Approach Driven by Quantized Nonlinear Waveforms. APCCAS 2006: 1959-1963 - [c23]George Hayashi, Akihiro Sawada, Takashi Morie, Kazuhiro Matsuyama, Ryangsu Kim, Seichiro Yoshida, Akinori Matsumoto, Katsumasa Hijikata, Kazuo Matsukawa, Yoshihiro Tamura, Jun Ogawa, Toshio Takita:
A 10.8mA Single Chip Transceiver for 430MHz Narrowband Systems in 0.15µm CMOS. ISSCC 2006: 1480-1489 - [c22]Shiro Dosho, Shiro Sakiyama, Noriaki Takeda, Yusuke Tokunaga, Takashi Morie:
A PLL for a DVD-16 Write System with 63 Output Phases and 32ps Resolution. ISSCC 2006: 2422-2431 - 2005
- [j10]Teppei Nakano, Takashi Morie, Makoto Nagata, Atsushi Iwata:
A Cellular-Automaton-Type Region Extraction Algorithm and its FPGA Implementation. J. Robotics Mechatronics 17(4): 378-386 (2005) - [c21]Osamu Nomura, Takashi Morie, Masakazu Matsugu, Atsushi Iwata:
A Convolutional Neural Network VLSI Architecture Using Sorting Model for Reducing Multiply-and-Accumulation Operations. ICNC (3) 2005: 1006-1014 - [c20]Teppei Nakano, Takashi Morie:
A digital LSI architecture of elastic graph matching and its FPGA implementation. IJCNN 2005: 689-694 - [c19]Youngjae Kim, Takashi Morie:
A pixel-parallel anisotropic diffusion algorithm for subjective contour generation. ISCAS (5) 2005: 4237-4240 - 2004
- [j9]Takashi Morie, Jun Umezawa, Atsushi Iwata:
Gabor-Type Filtering using Transient States of Cellular Neural Networks. Intell. Autom. Soft Comput. 10(2): 95-104 (2004) - [j8]Keisuke Korekado, Takashi Morie, Osamu Nomura, Hiroshi Ando, Teppei Nakano, Masakazu Matsugu, Atsushi Iwata:
A VLSI convolutional neural network for image recognition using merged/mixed analog-digital architecture. J. Intell. Fuzzy Syst. 15(3-4): 173-179 (2004) - [c18]Kouichi Nagano, Koji Okamoto, Akira Yamamoto, Hiroki Mouri, Akira Kawabe, Hirokuni Fujiyama, Takashi Morie, Hiroyuki Nakahira, Masahiro Kuramochi, Minoru Ochiai, Kazutoshi Aida, Youichi Ogura, Toshihiko Takahashi, Toru Kakiage, Masao Takiguchi, Takashi Yamamoto, Hiroshi Kamiyama, Yutaka Katabe:
A 0.13um CMOS ultra-compact DVD SoC employing a full digital equalizing PRML read channel. CICC 2004: 283-286 - [c17]Osamu Nomura, Takashi Morie, Keisuke Korekado, Masakazu Matsugu, Atsushi Iwata:
A Convolutional Neural Network VLSI Architecture Using Thresholding and Weight Decomposition. KES 2004: 995-1001 - 2003
- [j7]Koji Okamoto, Takashi Morie, Akira Yamamoto, Kouichi Nagano, Koji Sushihara, Hiroyuki Nakahira, Ryusuke Horibe, Kazutoshi Aida, Toshihiko Takahashi, Minoru Ochiai, Akinobu Soneda, Toru Kakiage, Tamaki Iwasaki, Hiroshi Taniuchi, Tadashi Shibata, Takahiro Ochi, Masao Takiguchi, Takashi Yamamoto, Tadayoshi Seike, Akira Matsuzawa:
A fully integrated 0.13-μm CMOS mixed-signal SoC for DVD player applications. IEEE J. Solid State Circuits 38(11): 1981-1991 (2003) - [c16]Keisuke Korekado, Takashi Morie, Osamu Nomura, Hiroshi Ando, Teppei Nakano, Masakazu Matsugu, Atsushi Iwata:
A Convolutional Neural Network VLSI for Image Recognition Using Merged/Mixed Analog-Digital Architecture. KES 2003: 169-176 - 2002
- [j6]Hiroshi Ando, Takashi Morie, Makoto Miyake, Makoto Nagata, Atsushi Iwata:
Image Segmentation/Extraction Using Nonlinear Cellular Networks and Their VLSI Implementation Using Pulse-Modulation Techniques. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(2): 381-388 (2002) - [j5]Shiro Dosho, Takashi Morie, Hirokuni Fujiyama:
A 200-MHz seventh-order equiripple continuous-time filter by design of nonlinearity suppression in 0.25-μm CMOS process. IEEE J. Solid State Circuits 37(5): 559-565 (2002) - [c15]Teppei Nakano, Takashi Morie, Makoto Nagata, Atsushi Iwata:
A cellular-automaton-type image extraction algorithm and its implementation using an FPGA. APCCAS (2) 2002: 197-200 - [c14]Makoto Nagata, Takashi Morie, Atsushi Iwata:
Modeling substrate noise generation in CMOS digital integrated circuits. CICC 2002: 501-504 - [c13]Makoto Nagata, Yoshitaka Murasaka, Youichi Nishimori, Takashi Morie, Atsushi Iwata:
Substrate Noise Analysis with Compact Digital Noise Injection and Substrate Models. ASP-DAC/VLSI Design 2002: 71-76 - 2001
- [j4]Makoto Nagata, Jin Nagai, Katsumasa Hijikata, Takashi Morie, Atsushi Iwata:
Physical design guides for substrate noise reduction in CMOS digital circuits. IEEE J. Solid State Circuits 36(3): 539-549 (2001) - [j3]Shigeo Kinoshita, Takashi Morie, Makoto Nagata, Atsushi Iwata:
A PWM analog memory programming circuit for floating-gate MOSFETs with 75-μs programming time and 11-bit updating resolution. IEEE J. Solid State Circuits 36(8): 1286-1290 (2001) - [c12]Makoto Nagata, Takafumi Ohmoto, Jin Nagai, Takashi Morie, Atsushi Iwata:
Test circuits for substrate noise evaluation in CMOS digital ICs. ASP-DAC 2001: 13-14 - [c11]Yoshitaka Murasaka, Makoto Nagata, Takafumi Ohmoto, Takashi Morie, Atsushi Iwata:
Chip-Level Substrate Noise Analysis with Network Reduction by Fundamental Matrix Computation. ISQED 2001: 482-487 - [c10]Takashi Morie, Tomohiro Matsuura, Makoto Nagata, Atsushi Iwata:
An Efficient Clustering Algorithm Using Stochastic Association Model and Its Implementation Using Nanostructures. NIPS 2001: 1115-1122 - 2000
- [j2]Makoto Nagata, Jin Nagai, Takashi Morie, Atsushi Iwata:
Measurements and analyses of substrate noise waveform inmixed-signal IC environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(6): 671-678 (2000) - [c9]Noriaki Takeda, Mitsuru Homma, Makoto Nagata, Takashi Morie, Atsushi Iwata:
A smart imager for the vision processing front-END. ASP-DAC 2000: 19-20 - [c8]Kenichi Murakoshi, Takashi Morie, Makoto Nagata, Atsushi Iwata:
An arbitrary chaos generator core curcuit using PWM/PPM signals. ASP-DAC 2000: 23-24 - [c7]Makoto Nagata, Jin Nagai, Takashi Morie, Atsushi Iwata:
Quantitative characterization of substrate noise for physical design guides in digital circuits. CICC 2000: 95-98 - [c6]Atsushi Iwata, Makoto Nagata, Noriaki Takeda, Mitsuru Homma, Takashi Morie:
Pulse modulation circuit architecture and its application to functional image sensors. ISCAS 2000: 301-304
1990 – 1999
- 1999
- [c5]Makoto Nagata, Yoji Kashima, Daisuke Tamura, Takashi Morie, Atsushi Iwata:
Measurements and analyses of substrate noise waveform in mixed signal IC environment. CICC 1999: 575-578 - [c4]Atsushi Iwata, Makoto Nagata, Hiroyuki Nakamoto, Noriaki Takeda, Mitsuru Homma, Hiroto Higashi, Takashi Morie:
A Feature Associative Processor for Image Recognition Based on A-D merged Architecture. VLSI 1999: 77-88 - 1998
- [c3]Souta Sakabayashi, Takashi Morie, Makoto Nagata, Atsushi Iwata:
Nonlinear Function Generators and Chaotic Signal Generators Based on Pulse-Phase Modulation. ICONIP 1998: 582-585 - [c2]Hiroshi Ando, Takashi Morie, Makoto Nagata, Atsushi Iwata:
Oscillator Networks for Image Segmentation and Their Circuits Using Pulse Modulation Method. ICONIP 1998: 586-589 - 1995
- [c1]Takashi Morie, Osamu Fujita, Kuniharu Uchimura:
Self-learning neural network LSI with high-resolution non-volatile analog memory. ICNN 1995: 1628-1632 - 1994
- [j1]Takashi Morie, Yoshihito Amemiya:
An all-analog expandable neural network LSI with on-chip backpropagation learning. IEEE J. Solid State Circuits 29(9): 1086-1093 (1994)
Coauthor Index
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