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2020 – today
- 2024
[j30]Haewoon Son, Hoyong Jung, Young-Chan Jang
:
A 1-kS/s 12-bit SAR ADC With Burst Conversion for Anti-Leakage Current. IEEE Access 12: 176094-176103 (2024)- [j29]Changmin Song, Hoyong Jung, KyoungSeop Chang, Kwanglae Cho, Seungyong Yoon, Young-Chan Jang:
A 24-Gb/s MIPI C-/D-PHY Receiver Bridge Chip With Phase Error Calibration Supporting FPGA-Based Frame Grabber. IEEE Trans. Very Large Scale Integr. Syst. 32(4): 714-727 (2024) - [c13]Dong-Seob Shin, Jong-Ho Park, Changmin Song, Seong-Yun Kim, Hyeonseok Lee, Jinyeong Lee, Young-Chan Jang:
Clock Recovery Circuit for 3-Gsymbol/s/lane MIPI C-PHY Receiver. ISOCC 2024: 45-46 - [c12]Jong-Ho Park, Minjun Cho, Juncheol Kim, Haewoon Son, Hyeon-Ho Kim, Young-Chan Jang:
3-Gsymbol/s/lane MIPI C-PHY Receiver with Feed-forward Level-dependent Equalization. ISOCC 2024: 49-50 - 2023
- [c11]Changmin Song, Minjun Cho, Sihan Kim, Young-Chan Jang:
4.5 Gsymbol/s/lane MIPI C-PHY Receiver with Channel Mismatch Calibration. ISCAS 2023: 1-4 - [c10]Sihan Kim, Changmin Song, Jinseok Kim, Yonghun Oh, Changwan Kim, Young-Chan Jang:
A 10-Gb/s Dual-Loop Reference-less CDR with FD Controller. ISOCC 2023: 109-110 - [c9]Haewoon Son, WonSeok Yang, Hoyong Jung, Young-Chan Jang:
1-kS/s 12-bit SAR ADC with Burst Conversion. ISOCC 2023: 295-296 - [c8]Hye-Min Shin, Hae-Won Son, Tai-Soon Park, Tae-Woo Oh, Young-Chan Jang:
First-order Continuous Time Delta-sigma Modulator with 3-bit SAR ADC and PNM DAC. ISOCC 2023: 297-298 - 2022
- [c7]Wonkyu Do, Neungin Jeon, Hoyong Jung, Young-Chan Jang:
Second-order Incremental Delta-sigma Modulator with 3-bit SAR ADC and Capacitor Sharing Scheme. ISOCC 2022: 39-40 - 2021
- [j28]Seokwon Choi, Changmin Song, Young-Chan Jang:
A 3.0 Gsymbol/s/lane MIPI C-PHY Receiver with Adaptive Level-Dependent Equalizer for Mobile CMOS Image Sensor. Sensors 21(15): 5197 (2021) - [c6]Hoyong Jung, Neungin Jeon, Young-Chan Jang:
Second-order Noise Shaping SAR ADC using 3-input Comparator with Voltage Gain Calibration. ISOCC 2021: 123-124 - [c5]Changmin Song, Se-Hyeon Cho, Young-Chan Jang:
A 0.2 ‒ 1.2GHz Adaptive Bandwidth PLL with Controllable KVCO. ISOCC 2021: 300-301 - 2020
- [j27]Pil-Ho Lee, Young-Chan Jang:
A 6.84 Gbps/lane MIPI C-PHY Transceiver Bridge Chip With Level-Dependent Equalization. IEEE Trans. Circuits Syst. 67-II(11): 2672-2676 (2020)
2010 – 2019
- 2019
- [j26]Jisu Son, Young-Chan Jang:
A 10-bit 10-MS/s single-ended asynchronous SAR ADC with CDAC boosting common-mode voltage and controlling input voltage range. IEICE Electron. Express 16(22): 20190597 (2019) - [j25]Pil-Ho Lee, Young-Chan Jang:
A 3Gbps/Lane MIPI D-PHY Transmission Buffer Chip. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 102-A(6): 783-787 (2019) - [j24]Pil-Ho Lee, Young-Chan Jang:
A 20-Gb/s Receiver Bridge Chip With Auto-Skew Calibration for MIPI D-PHY Interface. IEEE Trans. Consumer Electron. 65(4): 484-492 (2019) - 2018
- [c4]Eunji Youn, Young-Chan Jang:
12-bit 20M-S/s SAR ADC using C-R DAC and Capacitor Calibration. ISOCC 2018: 1-2 - 2017
- [j23]Ho-Seong Kim, Pil-Ho Lee, Jin-Wook Han, Seung-Hun Shin, Seung-Wuk Baek, Doo-Ill Park, Yongkyu Seo, Young-Chan Jang:
A 10 Gbps D-PHY Transmitter Bridge Chip for FPGA-Based Frame Generator Supporting MIPI DSI of Mobile Display. IEICE Trans. Electron. 100-C(11): 1035-1038 (2017) - [j22]Pil-Ho Lee, Han-Yeol Lee, Yeong-Woong Kim, Han-Young Hong, Young-Chan Jang:
A 10-Gbps receiver bridge chip with deserializer for FPGA-based frame grabber supporting MIPI CSI-2. IEEE Trans. Consumer Electron. 63(3): 209-215 (2017) - [j21]Pil-Ho Lee, Han-Yeol Lee, Hyun Bae Lee, Young-Chan Jang:
An On-Chip Monitoring Circuit for Signal-Integrity Analysis of 8-Gb/s Chip-to-Chip Interfaces With Source-Synchronous Clock. IEEE Trans. Very Large Scale Integr. Syst. 25(4): 1386-1396 (2017) - [c3]Seung-Hun Shin, Pil-Ho Lee, Jin-Woo Park, Yu-Jeong Hwang, Young-Chan Jang:
0.5 kHz-32 MHz digital fractional-N frequency synthesizer with burst-frequency switch. ISCAS 2017: 1-4 - [c2]Jin-Wook Han, Pil-Ho Lee, Yeong-Woong Kim, Sang-Dong Kim, Jin-Woo Park, Young-Chan Jang:
A clock recovery for 2.56 GSymbol/s MIPI C-PHY receiver. ISOCC 2017: 246-247 - 2016
- [j20]Pil-Ho Lee, Yu-Jeong Hwang, Han-Yeol Lee, Hyun Bae Lee, Young-Chan Jang:
An On-Chip Monitoring Circuit with 51-Phase PLL-Based Frequency Synthesizer for 8-Gb/s ODR Single-Ended Signaling Integrity Analysis. IEICE Trans. Electron. 99-C(4): 440-443 (2016) - [j19]Sang-Min Park, Yeon-Ho Jeong, Yu-Jeong Hwang, Pil-Ho Lee, Yeong-Woong Kim, Jisu Son, Han-Yeol Lee, Young-Chan Jang:
A 10-bit 20-MS/s Asynchronous SAR ADC with Meta-Stability Detector Using Replica Comparators. IEICE Trans. Electron. 99-C(6): 651-654 (2016) - 2014
- [j18]Pil-Ho Lee, Hyun Bae Lee, Young-Chan Jang:
A 125MHz 64-Phase Delay-Locked Loop with Coarse-Locking Circuit Independent of Duty Cycle. IEICE Trans. Electron. 97-C(5): 463-467 (2014) - [j17]Mungyu Kim, Hoon-Ju Chung, Young-Chan Jang:
A 10-bit CMOS Digital-to-Analog Converter with Compact Size for Display Applications. IEICE Trans. Electron. 97-C(6): 519-525 (2014) - [j16]Kwang-Hun Lee, Young-Chan Jang:
A 2-Gb/s CMOS SLVS Transmitter with Asymmetric Impedance Calibration for Mobile Interfaces. IEICE Trans. Electron. 97-C(8): 837-840 (2014) - 2013
- [j15]Ji-Hun Eo, Yeon-Ho Jeong, Young-Chan Jang:
An 8-Bit 100-kS/s CMOS Single-Ended SA ADC for 8×8 Point EEG/MEG Acquisition System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(2): 453-458 (2013) - 2012
- [j14]Han-Yeol Lee, Young-Chan Jang:
A true single-phase clocked flip-flop with leakage current compensation. IEICE Electron. Express 9(23): 1807-1812 (2012) - [j13]Hyun Bae Lee, Young-Chan Jang:
Mirrored Serpentine Microstrip Lines for Reduction of Far-End Crosstalk. IEICE Trans. Electron. 95-C(6): 1086-1088 (2012) - [j12]Ji-Hun Eo, Sang-Hun Kim, Mungyu Kim, Young-Chan Jang:
A 1.8 V 40-MS/sec 10-bit 0.18-㎛ CMOS Pipelined ADC using a Bootstrapped Switch with Constant Resistance. J. Inform. and Commun. Convergence Engineering 10(1): 85-90 (2012) - [j11]Kwang-Hun Lee, Young-Chan Jang:
A 1.8 V 0.18-μm 1 GHz CMOS Fast-Lock Phase-Locked Loop using a Frequency-to-Digital Converter. J. Inform. and Commun. Convergence Engineering 10(2): 187-193 (2012) - 2011
- [j10]Young-Chan Jang:
A Self-Calibrating Per-Pin Phase Adjuster for Source Synchronous Double Data Rate Signaling in Parallel Interface. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(2): 633-638 (2011) - [j9]Sang-Hun Kim, Yong-Hwan Lee, Hoon-Ju Chung, Young-Chan Jang:
A Bootstrapped Analog Switch with Constant On-Resistance. IEICE Trans. Electron. 94-C(6): 1069-1071 (2011) - [j8]Ji-Hun Eo, Sang-Hun Kim, Young-Chan Jang:
A 1 V 200 kS/s 10-bit Successive Approximation ADC for a Sensor Interface. IEICE Trans. Electron. 94-C(11): 1798-1801 (2011) - 2010
- [j7]Young-Chan Jang:
A digital phase corrector with a duty cycle detector and transmitter for a Quad Data Rate I/O scheme. IEICE Electron. Express 7(3): 146-152 (2010) - [j6]Young-Chan Jang:
An unmatched source synchronous I/O link for jitter reduction in a multi-phase clock system. IEICE Electron. Express 7(11): 797-803 (2010) - [j5]Young-Chan Jang:
A Swing Level Controlled Transmitter for Single-Ended Signaling with Center-Tapped Termination. IEICE Trans. Electron. 93-C(6): 861-863 (2010)
2000 – 2009
- 2009
- [j4]Young-Chan Jang, Hoeju Chung, Youngdon Choi, Hwan-Wook Park, Jaekwan Kim, Soouk Lim, Jung Sunwoo, Moon-Sook Park, Hyung-Seuk Kim, Sang-Yun Kim, Yun-Sang Lee, Woo-Seop Kim, Jung-Bae Lee, Jei-Hwan Yoo, Changhyun Kim:
BER Measurement of a 5.8-Gb/s/pin Unidirectional Differential I/O for DRAM Application With DIMM Channel. IEEE J. Solid State Circuits 44(11): 2987-2998 (2009) - 2007
- [j3]Young-Chan Jang, Jun-Hyun Bae, Sang-Hune Park, Jae-Yoon Sim, Hong-June Park:
An 8.8-GS/s 6-bit CMOS Time-Interleaved Flash Analog-to-Digital Converter with Multi-Phase Clock Generator. IEICE Trans. Electron. 90-C(6): 1156-1164 (2007) - [j2]Kyu-Hyoun Kim, Hoeju Chung, Woo-Seop Kim, Moon-Sook Park, Young-Chan Jang, Jinyoung Kim, Hwan-Wook Park, Uksong Kang, Paul W. Coteus, Joo-Sun Choi, Changhyun Kim:
An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme. IEEE J. Solid State Circuits 42(1): 193-200 (2007) - 2006
- [j1]Young-Chan Jang, Jun-Hyun Bae, Hong-June Park:
A Digital CMOS PWCL With Fixed-Delay Rising Edge and Digital Stability Control. IEEE Trans. Circuits Syst. II Express Briefs 53-II(10): 1063-1067 (2006) - [c1]Kyu-Hyoun Kim, Uksong Kang, Hoeju Chung, Dukha Park, Woo-Seop Kim, Young-Chan Jang, Moon-Sook Park, Hoon Lee, Jinyoung Kim, Jung Sunwoo, Hwan-Wook Park, Hyun-Kyung Kim, Su-Jin Chung, Jae-Kwan Kim, Hyung-Seuk Kim, Kee-Won Kwon, Young-Taek Lee, Joo-Sun Choi, Changhyun Kim:
An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme. ISSCC 2006: 527-536
Coauthor Index
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