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2000 – 2009
- 2009
[j6]Steven C. Chan, Phillip J. Restle, Thomas J. Bucelot, John S. Liberty, Stephen Weitzel, John M. Keaty, Brian K. Flachs, Richard Volant, Peter Kapusta, Jeffrey S. Zimmerman:
A Resonant Global Clock Distribution for the Cell Broadband Engine Processor. IEEE J. Solid State Circuits 44(1): 64-72 (2009)- 2008
- [c7]Steven C. Chan, Phillip J. Restle, Thomas J. Bucelot, Steve Weitzel, John M. Keaty, John S. Liberty, Brian K. Flachs, Richard Volant, Peter Kapusta, Jeffrey S. Zimmerman:
A Resonant Global Clock Distribution for the Cell Broadband-Engine Processor. ISSCC 2008: 512-513 - 2007
- [j5]Brian K. Flachs, Shigehiro Asano, Sang H. Dhong, H. Peter Hofstee, Gilles Gervais, Roy Kim, Tien Le, Peichun Liu, Jens Leenstra, John S. Liberty, Brad W. Michael, Hwa-Joon Oh, Silvia M. Müller, Osamu Takahashi, Koji Hirairi, Atsushi Kawasumi, Hiroaki Murakami, Hiromi Noro, Shoji Onishi, Juergen Pille, Joel Silberman, Suksoon Yong, Akiyuki Hatakeyama, Yukio Watanabe, Naoka Yano, Daniel A. Brokenshire, Mohammad Peyravian, VanDung To, Eiji Iwata:
Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI. IBM J. Res. Dev. 51(5): 529-544 (2007) - [c6]Osamu Takahashi, Erwin Behnen, Scott R. Cottier, Paula K. Coulman, Sang H. Dhong, Brian K. Flachs, H. Peter Hofstee, C. J. Johnson, Stephen D. Posluszny:
Cell Broadband Engine Processor Design Methodology. CICC 2007: 711-716 - [c5]Mack W. Riley, Brian K. Flachs, Sang H. Dhong, Gilles Gervais, Steve Weitzel, Michael Wang, David Boerstler, Mark Bolliger, John M. Keaty, Jürgen Pille, R. Berry, Osamu Takahashi, Y. Nishino, T. Uchino:
Implementation of the 65nm Cell Broadband Engine. CICC 2007: 717-720 - 2006
- [j4]Brian K. Flachs, Shigehiro Asano, Sang H. Dhong, H. Peter Hofstee, Gilles Gervais, Roy Kim, Tien Le, Peichun Liu, Jens Leenstra, John S. Liberty, Brad W. Michael, Hwa-Joon Oh, Silvia Melitta Müller, Osamu Takahashi, A. Hatakeyama, Yukio Watanabe, Naoka Yano, Daniel A. Brokenshire, Mohammad Peyravian, Vandung To, Eiji Iwata:
The microarchitecture of the synergistic processor for a cell processor. IEEE J. Solid State Circuits 41(1): 63-70 (2006) - [j3]Michael Gschwind, H. Peter Hofstee, Brian K. Flachs, Martin Hopkins, Yukio Watanabe, Takeshi Yamazaki:
Synergistic Processing in Cell's Multicore Architecture. IEEE Micro 26(2): 10-24 (2006) - 2005
- [j2]Osamu Takahashi, Scott R. Cottier, Sang H. Dhong, Brian K. Flachs, Joel Silberman:
Power-Conscious Design of the Cell Processor's Synergistic Processor Element. IEEE Micro 25(5): 10-18 (2005) - [c4]Osamu Takahashi, Russ Cook, Scott R. Cottier, Sang H. Dhong, Brian K. Flachs, Koji Hirairi, Atsushi Kawasumi, Hiroaki Murakami, Hiromi Noro, Hwa-Joon Oh, S. Onish, Juergen Pille, Joel Silberman:
The circuit design of the synergistic processor element of a CELL processor. ICCAD 2005: 111-117 - 2000
- [c3]Stephen D. Posluszny, Naoaki Aoki, David Boerstler, Paula K. Coulman, Sang H. Dhong, Brian K. Flachs, H. Peter Hofstee, Nobuo Kojima, Ohsang Kwon, Kyung T. Lee, David Meltzer, Kevin J. Nowka
, J. Park, J. Peter, Joel Silberman, Osamu Takahashi, Paul Villarrubia:
"Timing closure by design, " a high frequency microprocessor design methodology. DAC 2000: 712-717
1990 – 1999
- 1998
- [j1]Samuel H. Russ, Jonathan Robinson, Brian K. Flachs, Bjørn Heckel:
The Hector Distributed Run-Time Environment. IEEE Trans. Parallel Distributed Syst. 9(11): 1102-1114 (1998) - 1996
- [c2]Jonathan Robinson, Samuel H. Russ, Brian K. Flachs, Bjørn Heckel:
A Task Migration Implementation of the Message-Passing Interface. HPDC 1996: 61-68 - [c1]Samuel H. Russ, Brian K. Flachs, Jonathan Robinson, Bjørn Heckel:
Hector: Automated Task Allocation for MPI. IPPS 1996: 344-348
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