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ORCIDShigehiro Asano
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2010 – 2019
- 2011
[c3]Takashi Yoshikawa, Fumihiko Hyuga, Masayuki Tokunaga, Yutaka Yamada, Shigehiro Asano:
FlexGrip™: A small and high-performance programmable hardware for highly sequential application. COOL Chips 2011: 1-3
2000 – 2009
- 2009
- [c2]Akira Kuroda, Mayuko Koezuka, Hidenori Matsuzaki, Takashi Yoshikawa, Shigehiro Asano:
Mapping method for dynamically reconfigurable architecture. ASP-DAC 2009: 757-762 - 2007
- [j3]Brian K. Flachs, Shigehiro Asano, Sang H. Dhong, H. Peter Hofstee, Gilles Gervais, Roy Kim, Tien Le, Peichun Liu, Jens Leenstra, John S. Liberty, Brad W. Michael, Hwa-Joon Oh, Silvia M. Müller, Osamu Takahashi, Koji Hirairi, Atsushi Kawasumi, Hiroaki Murakami, Hiromi Noro, Shoji Onishi, Juergen Pille, Joel Silberman, Suksoon Yong, Akiyuki Hatakeyama, Yukio Watanabe, Naoka Yano, Daniel A. Brokenshire, Mohammad Peyravian, VanDung To, Eiji Iwata:
Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI. IBM J. Res. Dev. 51(5): 529-544 (2007) - 2006
- [j2]Brian K. Flachs, Shigehiro Asano, Sang H. Dhong, H. Peter Hofstee, Gilles Gervais, Roy Kim, Tien Le, Peichun Liu, Jens Leenstra, John S. Liberty, Brad W. Michael, Hwa-Joon Oh, Silvia Melitta Müller, Osamu Takahashi, A. Hatakeyama, Yukio Watanabe, Naoka Yano, Daniel A. Brokenshire, Mohammad Peyravian, Vandung To, Eiji Iwata:
The microarchitecture of the synergistic processor for a cell processor. IEEE J. Solid State Circuits 41(1): 63-70 (2006) - [c1]Takashi Yoshikawa, Yutaka Yamada, Shigehiro Asano:
An implementation of hardware accelerator using dynamically reconfigurable architecture. Hot Chips Symposium 2006: 1-38 - 2005
- [j1]Seiji Maeda, Shigehiro Asano, Tomofumi Shimada, Koichi Awazu, Haruyuki Tago:
A Real-Time Software Platform for the Cell Processor. IEEE Micro 25(5): 20-29 (2005)
Coauthor Index
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