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2010 – 2019
- 2018
[c7]Dennis Sylvester, Koji Hirairi, Edith Beigné:
Session 18 overview: Adaptive circuits and digital regulators: Digital circuit techniques subcommittee. ISSCC 2018: 298-299- 2013
- [j3]Hiroshi Fuketa, Koji Hirairi, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai:
Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: VDDmin-Aware Dual Supply Voltage Technique. IEEE Trans. Very Large Scale Integr. Syst. 21(6): 1175-1179 (2013) - 2012
- [c6]Tadashi Yasufuku, Koji Hirairi, Yu Pu, Yun Fei Zheng, Ryo Takahashi, Masato Sasaki, Hiroshi Fuketa, Atsushi Muramatsu, Masahiro Nomura, Hirofumi Shinohara, Makoto Takamiya, Takayasu Sakurai:
24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in VDDmin limited ultra low voltage logic circuits. ISQED 2012: 586-591 - [c5]Koji Hirairi, Yasuyuki Okuma, Hiroshi Fuketa, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai:
13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully integrated digital LDO. ISSCC 2012: 486-488 - 2011
- [c4]Tadashi Yasufuku, Satoshi Iida, Hiroshi Fuketa, Koji Hirairi, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai:
Investigation of determinant factors of minimum operating voltage of logic gates in 65-nm CMOS. ISLPED 2011: 21-26 - [c3]Hiroshi Fuketa, Koji Hirairi, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai:
12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (VDD) scaling from 1.2v to 310mv enabled by contention-less flip-flops (CLFF) and separated VDD between flip-flops and combinational logics. ISLPED 2011: 163-168 - 2010
- [c2]Yu Pu, Xin Zhang, Jim Huang, Atsushi Muramatsu, Masahiro Nomura, Koji Hirairi, Hidehiro Takata, Taro Sakurabayashi, Shinji Miyano, Makoto Takamiya, Takayasu Sakurai:
Misleading energy and performance claims in sub/near threshold digital systems. ICCAD 2010: 625-631
2000 – 2009
- 2007
- [j2]Brian K. Flachs, Shigehiro Asano, Sang H. Dhong, H. Peter Hofstee, Gilles Gervais, Roy Kim, Tien Le, Peichun Liu, Jens Leenstra, John S. Liberty, Brad W. Michael, Hwa-Joon Oh, Silvia M. Müller, Osamu Takahashi, Koji Hirairi, Atsushi Kawasumi, Hiroaki Murakami, Hiromi Noro, Shoji Onishi, Juergen Pille, Joel Silberman, Suksoon Yong, Akiyuki Hatakeyama, Yukio Watanabe, Naoka Yano, Daniel A. Brokenshire, Mohammad Peyravian, VanDung To, Eiji Iwata:
Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI. IBM J. Res. Dev. 51(5): 529-544 (2007) - 2006
- [j1]James D. Warnock, Dieter F. Wendel, Tony Aipperspach, Erwin Behnen, Robert A. Cordes, Sang H. Dhong, Koji Hirairi, Hiroaki Murakami, Shohji Onishi, Dac C. Pham, Jürgen Pille, Stephen D. Posluszny, Osamu Takahashi, Huajun Wen:
Circuit Design Techniques for a First-Generation Cell Broadband Engine Processor. IEEE J. Solid State Circuits 41(8): 1692-1706 (2006) - 2005
- [c1]Osamu Takahashi, Russ Cook, Scott R. Cottier, Sang H. Dhong, Brian K. Flachs, Koji Hirairi, Atsushi Kawasumi, Hiroaki Murakami, Hiromi Noro, Hwa-Joon Oh, S. Onish, Juergen Pille, Joel Silberman:
The circuit design of the synergistic processor element of a CELL processor. ICCAD 2005: 111-117
Coauthor Index
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