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ORCIDMack W. Riley
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2000 – 2009
- 2008
[c7]Osamu Takahashi, Chad Adams, D. Ault, Erwin Behnen, O. Chiang, Scott R. Cottier, Paula K. Coulman, James Culp, Gilles Gervais, M. S. Gray, Y. Itaka, C. J. Johnson, Fumihiro Kono, L. Maurice, Kevin W. McCullen
, Lam Nguyen, Y. Nishino, Hiromi Noro, Jürgen Pille, Mack W. Riley, M. Shen, Chiaki Takano, Shunsako Tokito, Tina Wagner, Hiroshi Yoshihara:
Migration of Cell Broadband Engine from 65nm SOI to 45nm SOI. ISSCC 2008: 86-87- 2007
- [j3]Mack W. Riley, Mike Genden:
Cell Broadband Engine Debugging for Unknown Events. IEEE Des. Test Comput. 24(5): 486-493 (2007) - [j2]Mack W. Riley, James D. Warnock, Dieter F. Wendel:
Cell Broadband Engine processor: Design and implementation. IBM J. Res. Dev. 51(5): 545-558 (2007) - [c6]Mack W. Riley, Brian K. Flachs, Sang H. Dhong, Gilles Gervais, Steve Weitzel, Michael Wang, David Boerstler, Mark Bolliger, John M. Keaty, Jürgen Pille, R. Berry, Osamu Takahashi, Y. Nishino, T. Uchino:
Implementation of the 65nm Cell Broadband Engine. CICC 2007: 717-720 - 2006
- [j1]Dac C. Pham, Tony Aipperspach, David Boerstler, Mark Bolliger, Rajat Chaudhry, Dennis Cox, Paul E. Harvey, H. Peter Hofstee, Charles R. Johns, Jim Kahle, Atsushi Kameyama, John M. Keaty, Yoshio Masubuchi, Mydung Pham, Jürgen Pille, Stephen D. Posluszny, Mack W. Riley, Daniel L. Stasiak, Masakazu Suzuoki, Osamu Takahashi, James D. Warnock, Stephen Weitzel, Dieter F. Wendel, Kazuaki Yazawa:
Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor. IEEE J. Solid State Circuits 41(1): 179-196 (2006) - [c5]Dac C. Pham, Hans-Werner Anderson, Erwin Behnen, Mark Bolliger, Sanjay Gupta, H. Peter Hofstee, Paul E. Harvey, Charles R. Johns, James A. Kahle, Atsushi Kameyama, John M. Keaty, Bob Le, Sang Lee, Tuyen V. Nguyen, John G. Petrovick, Mydung Pham, Juergen Pille, Stephen D. Posluszny, Mack W. Riley, Joseph Verock, James D. Warnock, Steve Weitzel, Dieter F. Wendel:
Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor. ASP-DAC 2006: 871-878 - [c4]Eskinder Hailu, David W. Boerstler, Kazuhiko Miki, Jieming Qi, Michael Wang, Mack W. Riley:
A Circuit for Reducing Large Transient Current Effects on Processor Power Grids. ISSCC 2006: 2238-2245 - [c3]Mack W. Riley, Nathan Chelstrom, Mike Genden, Shoji Sawamura:
Debug of the CELL Processor: Moving the Lab into Silicon. ITC 2006: 1-9 - 2005
- [c2]Dac C. Pham, Erwin Behnen, Mark Bolliger, H. Peter Hofstee, Charles R. Johns, James A. Kahle, Atsushi Kameyama, John M. Keaty, Bob Le, Yoshio Masubuchi, Stephen D. Posluszny, Mack W. Riley, Masakazu Suzuoki, Michael Wang, James D. Warnock, Steve Weitzel, Dieter F. Wendel, Kazuaki Yazawa:
The design methodology and implementation of a first-generation CELL processor: a multi-core SoC. CICC 2005: 45-49 - [c1]Mack W. Riley, Louis B. Bushard, Nathan Paul Chelstrom, Naoki Kiryu, Steven Ross Ferguson:
Testability features of the first-generation CELL processor. ITC 2005: 9
Coauthor Index
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