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ORCIDDavid M. Bull
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2010 – 2019
- 2019
[c14]Zacharias Hadjilambrou, Shidhartha Das, Paul N. Whatmough, David M. Bull, Yiannakis Sazeides:
GeST: An Automatic Framework For Generating CPU Stress-Tests. ISPASS 2019: 1-10- 2017
- [j7]Paul N. Whatmough
, Shidhartha Das, Zacharias Hadjilambrou, David M. Bull:
Power Integrity Analysis of a 28 nm Dual-Core ARM Cortex-A57 Cluster Using an All-Digital Power Delivery Monitor. IEEE J. Solid State Circuits 52(6): 1643-1654 (2017) - 2015
- [c13]Paul N. Whatmough, Shidhartha Das, David M. Bull:
Analysis of adaptive clocking technique for resonant supply voltage noise mitigation. ISLPED 2015: 128-133 - [c12]Shidhartha Das, Paul N. Whatmough, David M. Bull:
Modeling and characterization of the system-level Power Delivery Network for a dual-core ARM Cortex-A57 cluster in 28nm CMOS. ISLPED 2015: 146-151 - [c11]Paul N. Whatmough, Shidhartha Das, Zacharias Hadjilambrou, David M. Bull:
14.6 An all-digital power-delivery monitor for analysis of a 28nm dual-core ARM Cortex-A57 cluster. ISSCC 2015: 1-3 - [c10]Paul N. Whatmough, George Smart, Shidhartha Das, Yiannis Andreopoulos, David M. Bull:
A 0.6V all-digital body-coupled wakeup transceiver for IoT applications. VLSIC 2015: 98- - 2014
- [j6]Paul N. Whatmough, Shidhartha Das, David M. Bull:
A Low-Power 1-GHz Razor FIR Accelerator With Time-Borrow Tracking Pipeline and Approximate Error Correction in 65-nm CMOS. IEEE J. Solid State Circuits 49(1): 84-94 (2014) - [j5]Shidhartha Das, Ganesh S. Dasika, Karthik Shivashankar, David M. Bull:
A 1 GHz Hardware Loop-Accelerator With Razor-Based Dynamic Adaptation for Energy-Efficient Operation. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(8): 2290-2298 (2014) - 2013
- [j4]Paul N. Whatmough, Shidhartha Das, David M. Bull, Izzat Darwazeh:
Circuit-Level Timing Error Tolerance for Low-Power DSP Filters and Transforms. IEEE Trans. Very Large Scale Integr. Syst. 21(6): 989-999 (2013) - [c9]Shidhartha Das, Ganesh S. Dasika, Karthik Shivashankar, David M. Bull:
A 1GHz hardware loop-accelerator with razor-based dynamic adaptation for energy-efficient operation. CICC 2013: 1-4 - [c8]Paul N. Whatmough, Shidhartha Das, David M. Bull:
A low-power 1GHz razor FIR accelerator with time-borrow tracking pipeline and approximate error correction in 65nm CMOS. ISSCC 2013: 428-429 - 2012
- [c7]Paul N. Whatmough, Shidhartha Das, David M. Bull, Izzat Darwazeh:
Selective time borrowing for DSP pipelines with hybrid voltage control loop. ASP-DAC 2012: 763-768 - 2011
- [j3]David M. Bull, Shidhartha Das, Karthik Shivashankar, Ganesh S. Dasika, Krisztián Flautner, David T. Blaauw:
A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation. IEEE J. Solid State Circuits 46(1): 18-31 (2011) - [j2]David M. Bull, Shidhartha Das, Karthik Shivashankar, Ganesh S. Dasika, Krisztián Flautner, David T. Blaauw:
Correction to "A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation". IEEE J. Solid State Circuits 46(3): 705 (2011) - [c6]Paul N. Whatmough, Shidhartha Das, David M. Bull, Izzat Darwazeh:
Error-resilient low-power DSP via path-delay shaping. DAC 2011: 1008-1013 - 2010
- [c5]Paul N. Whatmough, Izzat Darwazeh, David M. Bull, Shidhartha Das, Danny Kershaw:
A robust FIR filter with in situ error detection. ISCAS 2010: 4185-4188 - [c4]David M. Bull, Shidhartha Das, Karthik Shivashankar, Ganesh S. Dasika, Krisztián Flautner, David T. Blaauw:
A power-efficient 32b ARM ISA processor using timing-error detection and correction for transient-error tolerance and adaptation to PVT variation. ISSCC 2010: 284-285
2000 – 2009
- 2009
- [j1]Shidhartha Das, Carlos Tokunaga, Sanjay Pant, Wei-Hsiang Ma, Sudherssen Kalaiselvan, Kevin Lai, David M. Bull, David T. Blaauw:
RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance. IEEE J. Solid State Circuits 44(1): 32-48 (2009) - [c3]Shidhartha Das, David T. Blaauw, David M. Bull, Krisztián Flautner, Rob Aitken:
Addressing design margins through error-tolerant circuits. DAC 2009: 11-12 - 2008
- [c2]Ganesh S. Dasika, Shidhartha Das, Kevin Fan, Scott A. Mahlke, David M. Bull:
DVFS in loop accelerators using BLADES. DAC 2008: 894-897 - [c1]David T. Blaauw, Sudherssen Kalaiselvan, Kevin Lai, Wei-Hsiang Ma, Sanjay Pant, Carlos Tokunaga, Shidhartha Das, David M. Bull:
Razor II: In Situ Error Detection and Correction for PVT and SER Tolerance. ISSCC 2008: 400-401
Coauthor Index
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