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2020 – today
- 2024
[c7]Uta Kobayashi, Yasuhiro Sugimoto, Koji Yoshimura, Kiichi Yamashita, Akira Yasuda:
A CSRR Glucose Concentration Sensor with Increased Resolution Using the Q-value Enhancement Circuit Technique. ICCE 2024: 1-4- [c6]Koji Yoshimura, Yasuhiro Sugimoto, Uta Kobayashi, Kiichi Yamashita, Akira Yasuda:
A Complementary Split Ring Resonator Sensor Optimized for Maximizing the Dip and Q-value in S21 Frequency Characteristics. ICCE 2024: 1-4 - 2023
- [c5]Haruka Sakohira, Kiichi Yamashita, Yoko Uwate, Yoshifumi Nishio:
Rewiring Effect of High Synchronization Edges in Complex Oscillator Networks. ISOCC 2023: 233-234 - [c4]Daiki Akai, Kiichi Yamashita, Yoko Uwate, Yoshifumi Nishio:
Synchoronization Penomena of Coupled Oscillators in Weighted Three-Dimensional Complex Networks. ISOCC 2023: 235-236 - 2022
- [c3]Kiichi Yamashita, Yoko Uwate, Yoshifumi Nishio:
Synchronization Phenomena of Coupled Oscillators with Node and Edge Weights in Two-Dimensional Complex Networks. ISOCC 2022: 280-281
2010 – 2019
- 2010
- [c2]Kenichi Ohhata, Hironori Imamura, Toshinobu Ohno, Takaya Taniguchi, Kiichi Yamashita, Toru Yazaki, Norio Chujo:
17 Gb/s VCSEL driver using double-pulse asymmetric emphasis technique in 90-nm CMOS for optical interconnection. ISCAS 2010: 1847-1850
2000 – 2009
- 2009
- [j7]Kenichi Ohhata, Koki Uchino, Yuichiro Shimizu, Kosuke Oyama, Kiichi Yamashita:
Design of a 770-MHz, 70-mW, 8-bit Subranging ADC Using Reference Voltage Precharging Architecture. IEEE J. Solid State Circuits 44(11): 2881-2890 (2009) - 2008
- [j6]Kenichi Ohhata, Yuichiro Shimizu, Kiichi Yamashita:
Feedthrough reduction technique for track-and-hold circuit with body-bias control circuit. IEICE Electron. Express 5(13): 478-482 (2008) - [j5]Takuma Nishimoto, Kiichi Yamashita, Kenichi Ohhata:
Sandwich Structure Type RF-MEMS Variable Capacitor with Low Voltage Controllability and Wide Tuning Range. IEICE Trans. Commun. 91-B(2): 572-574 (2008) - 2007
- [j4]Kenichi Ohhata, Kosuke Yayama, Yuichiro Shimizu, Kiichi Yamashita:
A 1-GHz, 56.3-dB SFDR CMOS track-and-hold circuit with body-bias control circuit. IEICE Electron. Express 4(22): 701-706 (2007) - 2006
- [j3]Kenichi Ohhata, Katsuyoshi Harasawa, Makoto Honda, Kiichi Yamashita:
Design of Low-Noise, Low-Power 10-GHz VCO Using 0.18-µm CMOS Technology. IEICE Trans. Electron. 89-C(2): 203-205 (2006)
1990 – 1999
- 1995
- [j2]Nobuo Kotera, Kiichi Yamashita, Keiichi Kitamura, Yasushi Hatta:
Constant-current circuit-biasing technology for GaAs FET IC. IEEE J. Solid State Circuits 30(1): 61-64 (1995)
1980 – 1989
- 1984
- [c1]Yoshitaka Takasaki, Kiichi Yamashita, Yasushi Takahashi, Yuji Nakano:
Instantaneous In-Service Fault Location Scheme For Digital Transmission Systems. ICC (3) 1984: 1484-1487
1970 – 1979
- 1976
- [j1]Yoshitaka Takasaki, Mitsuo Tanaka, Narimichi Maeda, Kiichi Yamashita, Katsuyuki Nagano:
Optical Pulse Formats for Fiber Optic Digital Communications. IEEE Trans. Commun. 24(4): 404-413 (1976)
Coauthor Index
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