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2020 – today
- 2022
[c15]Stafford Hutchins, Jiabo Li, Atresh Sanne, Zhanping Chen, Mohammad M. Hasan, Uddalak Bhattacharya, Eric Karl, Jaydeep P. Kulkarni:
A High Output Power 1V Charge Pump and Power Switch for Configurable, In-Field-Programmable Metal eFuse on Intel 4 Logic Technology. VLSI Technology and Circuits 2022: 136-137
2010 – 2019
- 2017
- [j13]Zhanping Chen
, Sarvesh H. Kulkarni, Vincent E. Dorgan, Salil Manohar Rajarshi, Lei Jiang, Uddalak Bhattacharya:
A 0.9-μm2 1T1R Bit Cell in 14-nm High-Density Metal Fuse Technology for High-Volume Manufacturing and In-Field Programming. IEEE J. Solid State Circuits 52(4): 933-939 (2017) - 2016
- [j12]Sarvesh H. Kulkarni, Zhanping Chen, Balaji Srinivasan, Brian Pedersen, Uddalak Bhattacharya, Kevin Zhang:
A High-Density Metal-Fuse Technology Featuring a 1.6 V Programmable Low-Voltage Bit Cell With Integrated 1 V Charge Pumps in 22 nm Tri-Gate CMOS. IEEE J. Solid State Circuits 51(4): 1003-1008 (2016) - [c14]Zhanping Chen, Sarvesh H. Kulkarni, Vincent E. Dorgan, Uddalak Bhattacharya, Kevin Zhang:
A 0.9um2 1T1R bit cell in 14nm SoC process for metal-fuse OTP array with hierarchical bitline, bit level redundancy, and power gating. VLSI Circuits 2016: 1-2 - 2015
- [c13]Sarvesh H. Kulkarni, Zhanping Chen, Balaji Srinivasan, Brian Pedersen, Uddalak Bhattacharya, Kevin Zhang:
Low-voltage metal-fuse technology featuring a 1.6V-programmable 1T1R bit cell with an integrated 1V charge pump in 22nm tri-gate process. VLSIC 2015: 174- - 2010
- [j11]Sarvesh H. Kulkarni, Zhanping Chen, Jun He, Lei Jiang, Brian Pedersen, Kevin Zhang:
A 4 kb Metal-Fuse OTP-ROM Macro Featuring a 2 V Programmable 1.37 μ m 2 1T1R Bit Cell in 32 nm High-k Metal-Gate CMOS. IEEE J. Solid State Circuits 45(4): 863-868 (2010)
2000 – 2009
- 2009
- [j10]Fatih Hamzaoglu, Kevin Zhang, Yih Wang, Hong Jo Ahn, Uddalak Bhattacharya, Zhanping Chen, Yong-Gee Ng, Andrei Pavlov, Ken Smits, Mark Bohr:
A 3.8 GHz 153 Mb SRAM Design With Dynamic Stability Enhancement and Leakage Reduction in 45 nm High-k Metal Gate CMOS Technology. IEEE J. Solid State Circuits 44(1): 148-154 (2009) - 2008
- [j9]Yih Wang, Hong Jo Ahn, Uddalak Bhattacharya, Zhanping Chen, Tom Coan, Fatih Hamzaoglu, Walid M. Hafez, Chia-Hong Jan, Pramod Kolar, Sarvesh H. Kulkarni, Jie-Feng Lin, Yong-Gee Ng, Ian Post, Liqiong Wei, Ying Zhang, Kevin Zhang, Mark Bohr:
A 1.1 GHz 12 µA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications. IEEE J. Solid State Circuits 43(1): 172-179 (2008) - [c12]Fatih Hamzaoglu, Kevin Zhang, Yih Wang, Hong Jo Ahn, Uddalak Bhattacharya, Zhanping Chen, Yong-Gee Ng, Andrei Pavlov, Ken Smits, Mark Bohr:
A 153Mb-SRAM Design with Dynamic Stability Enhancement and Leakage Reduction in 45nm High-Κ Metal-Gate CMOS Technology. ISSCC 2008: 376-377 - 2006
- [j8]Kevin Zhang, Uddalak Bhattacharya, Zhanping Chen, Fatih Hamzaoglu, Daniel Murray, Narendra Vallepalli, Yih Wang, Bo Zheng, Mark Bohr:
A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply. IEEE J. Solid State Circuits 41(1): 146-151 (2006) - 2005
- [j7]Kevin Zhang, Uddalak Bhattacharya, Zhanping Chen, Fatih Hamzaoglu, Daniel Murray, Narendra Vallepalli, Yih Wang, Bo Zheng, Mark Bohr:
SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction. IEEE J. Solid State Circuits 40(4): 895-901 (2005) - 2002
- [j6]Zhanping Chen, Liqiong Wei, Ali Keshavarzi, Kaushik Roy:
IDDQ Testing for Deep-Submicron ICs: Challenges and Solutions. IEEE Des. Test Comput. 19(2): 24-33 (2002) - [j5]Liqiong Wei, Rongtian Zhang, Kaushik Roy, Zhanping Chen, David B. Janes:
Vertically integrated SOI circuits for low-power and high-performance applications. IEEE Trans. Very Large Scale Integr. Syst. 10(3): 351-362 (2002) - [c11]Zhanping Chen, Liqiong Wei, Ali Keshavarzi, Kaushik Roy:
IDDQ Testing for Deep Submicron ICs: Challenges and Solutions. LATW 2002: 186-192 - 2001
- [j4]Zhanping Chen, Liqiong Wei, Kaushik Roy:
On effective IDDQ testing of low-voltage CMOS circuits using leakage control techniques. IEEE Trans. Very Large Scale Integr. Syst. 9(5): 718-725 (2001) - [c10]James W. Tschanz, Siva G. Narendra, Zhanping Chen, Shekhar Borkar, Manoj Sachdev, Vivek De:
Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors. ISLPED 2001: 147-152 - 2000
- [j3]Zhanping Chen, Kaushik Roy, Edwin K. P. Chong:
Estimation of power dissipation using a novel power macromodelingtechnique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(11): 1363-1369 (2000) - [c9]Zhanping Chen, Liqiong Wei, Kaushik Roy:
On Effective IDDQ Testing of Low Voltage CMOS Circuits Using Leakage Control Techniques. ISQED 2000: 181-188
1990 – 1999
- 1999
- [j2]Liqiong Wei, Zhanping Chen, Kaushik Roy, Mark C. Johnson, Yibin Ye, Vivek De:
Design and optimization of dual-threshold circuits for low-voltage low-power applications. IEEE Trans. Very Large Scale Integr. Syst. 7(1): 16-24 (1999) - [c8]Liqiong Wei, Zhanping Chen, Kaushik Roy, Yibin Ye, Vivek De:
Mixed-Vth (MVT) CMOS Circuit Design Methodology for Low Power Applications. DAC 1999: 430-435 - [c7]Kaushik Roy, Liqiong Wei, Zhanping Chen:
Multiple-Vdd multiple-Vth CMOS (MVCMOS) for low power applications. ISCAS (1) 1999: 366-370 - 1998
- [j1]Zhanping Chen, Kaushik Roy, Tan-Li Chou:
Efficient statistical approach to estimate power considering uncertain properties of primary inputs. IEEE Trans. Very Large Scale Integr. Syst. 6(3): 484-492 (1998) - [c6]Zhanping Chen, Kaushik Roy, Yibin Ye:
Estimation of average switching power under accurate modeling of signal correlations. CICC 1998: 507-510 - [c5]Liqiong Wei, Zhanping Chen, Mark Johnson, Kaushik Roy, Vivek De:
Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits. DAC 1998: 489-494 - [c4]Zhanping Chen, Kaushik Roy:
A Power Macromodeling Technique Based on Power Sensitivity. DAC 1998: 678-683 - [c3]Zhanping Chen, Kaushik Roy, Edwin K. P. Chong:
Estimation of power sensitivity in sequential circuits with power macromodeling application. ICCAD 1998: 468-472 - [c2]Zhanping Chen, Mark Johnson, Liqiong Wei, Kaushik Roy:
Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks. ISLPED 1998: 239-244 - 1997
- [c1]Zhanping Chen, Kaushik Roy, Tan-Li Chou:
Power sensitivity - a new method to estimate power dissipation considering uncertain specifications of primary inputs. ICCAD 1997: 40-44
Coauthor Index
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