"A 0.9um2 1T1R bit cell in 14nm SoC process for metal-fuse OTP ..."

Zhanping Chen et al. (2016)

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DOI: 10.1109/VLSIC.2016.7573506

access: closed

type: Conference or Workshop Paper

metadata version: 2024-04-26

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Zhanping Chen, Sarvesh H. Kulkarni, Vincent E. Dorgan, Uddalak Bhattacharya, Kevin Zhang:
A 0.9um² 1T1R bit cell in 14nm SoC process for metal-fuse OTP array with hierarchical bitline, bit level redundancy, and power gating. VLSI Circuits 2016: 1-2

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