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2000 – 2009
- 2009
[j7]Blaine A. Stackhouse, Sal Bhimji, Chris Bostak, Dave Bradley, Brian S. Cherkauer, Jayen Desai, Erin Francom, Mike Gowan, Paul E. Gronowski, Dan Krueger, Charles Morganti, Steve Troyer:
A 65 nm 2-Billion Transistor Quad-Core Itanium Processor. IEEE J. Solid State Circuits 44(1): 18-31 (2009)- 2008
- [c3]Blaine A. Stackhouse, Brian S. Cherkauer, Michael K. Gowan, Paul E. Gronowski, Chris Lyles:
A 65nm 2-Billion-Transistor Quad-Core Itanium® Processor. ISSCC 2008: 92-93 - 2007
- [j6]Stefan Rusu, Simon M. Tam, Harry Muljono, David Ayers, Jonathan Chang, Brian S. Cherkauer, Jason Stinson, John Benoit, Raj Varada, Justin Leung, Rahul Dilip Limaye, Sujal Vora:
A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache. IEEE J. Solid State Circuits 42(1): 17-25 (2007) - 2004
- [j5]Stefan Rusu, Harry Muljono, Brian S. Cherkauer:
Itanium 2 Processor 6M: Higher Frequency and Larger L3 Cache. IEEE Micro 24(2): 10-18 (2004) - 2003
- [j4]Stefan Rusu, Jason Stinson, Simon Tam, Justin Leung, Harry Muljono, Brian S. Cherkauer:
A 1.5-GHz 130-nm Itanium® 2 Processor with 6-MB on-die L3 cache. IEEE J. Solid State Circuits 38(11): 1887-1895 (2003)
1990 – 1999
- 1995
- [j3]Brian S. Cherkauer, Eby G. Friedman:
Design of tapered buffers with local interconnect capacitance. IEEE J. Solid State Circuits 30(2): 151-155 (1995) - [j2]Brian S. Cherkauer, Eby G. Friedman:
A unified design methodology for CMOS tapered buffers. IEEE Trans. Very Large Scale Integr. Syst. 3(1): 99-111 (1995) - 1994
- [j1]Brian S. Cherkauer, Eby G. Friedman:
Channel width tapering of serially connected MOSFET's with emphasis on power dissipation. IEEE Trans. Very Large Scale Integr. Syst. 2(1): 100-114 (1994) - [c2]Brian S. Cherkauer, Eby G. Friedman:
Unification of Speed, Power, Area & Reliability in CMOS Tapered Buffer Design. ISCAS 1994: 111-114 - 1993
- [c1]Brian S. Cherkauer, Eby G. Friedman:
The Effects of Channel Width Tapering on the Power Dissipation of Serially Connected MOSFETs. ISCAS 1993: 2110-2113
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