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2010 – 2019
- 2019
[j4]Mohamed Arafa
, Bahaa Fahim, Sailesh Kottapalli, Akhilesh Kumar, Lily Pao Looi, Sreenivas Mandava, Andy Rudoff, Ian M. Steiner, Bob Valentine, Geetha Vedaraman, Sujal Vora:
Cascade Lake: Next Generation Intel Xeon Scalable Processor. IEEE Micro 39(2): 29-36 (2019)- 2018
- [c5]Simon M. Tam, Harry Muljono, Min Huang, Sitaraman Iyer, Kalapi Royneogi, Nagmohan Satti, Rizwan Qureshi, Wei Chen, Tom Wang, Hubert Hsieh, Sujal Vora, Eddie Wang:
SkyLake-SP: A 14nm 28-Core xeon® processor. ISSCC 2018: 34-36 - 2015
- [j3]Stefan Rusu, Harry Muljono, David Ayers, Simon M. Tam, Wei Chen, Aaron Martin, Shenggao Li, Sujal Vora, Raj Varada, Eddie Wang:
A 22 nm 15-Core Enterprise Xeon® Processor Family. IEEE J. Solid State Circuits 50(1): 35-48 (2015) - 2014
- [c4]Stefan Rusu, Harry Muljono, David Ayers, Simon M. Tam, Wei Chen, Aaron Martin, Shenggao Li, Sujal Vora, Raj Varada, Eddie Wang:
5.4 Ivytown: A 22nm 15-core enterprise Xeon® processor family. ISSCC 2014: 102-103 - 2013
- [c3]P. Pant, M. Amodeo, Sujal Vora, Jonathon E. Colburn:
Innovative practices session 10C: Delay test. VTS 2013: 1 - 2010
- [j2]Stefan Rusu, Simon M. Tam, Harry Muljono, Jason Stinson, David Ayers, Jonathan Chang, Raj Varada, Matt Ratta, Sailesh Kottapalli, Sujal Vora:
A 45 nm 8-Core Enterprise Xeon¯ Processor. IEEE J. Solid State Circuits 45(1): 7-14 (2010)
2000 – 2009
- 2009
- [c2]Stefan Rusu, Simon M. Tam, Harry Muljono, Jason Stinson, David Ayers, Jonathan Chang, Raj Varada, Matt Ratta, Sailesh Kottapalli, Sujal Vora:
Power reduction techniques for an 8-core xeon® processor. ESSCIRC 2009: 340-343 - 2007
- [j1]Stefan Rusu, Simon M. Tam, Harry Muljono, David Ayers, Jonathan Chang, Brian S. Cherkauer, Jason Stinson, John Benoit, Raj Varada, Justin Leung, Rahul Dilip Limaye, Sujal Vora:
A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache. IEEE J. Solid State Circuits 42(1): 17-25 (2007) - 2006
- [c1]Simon Tam, Justin Leung, Rahul Dilip Limaye, Sam Choy, Sujal Vora, Mitsuhiro Adachi:
Clock Generation and Distribution of a Dual-Core Xeon Processor with 16MB L3 Cache. ISSCC 2006: 1512-1521
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