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ORCIDSailesh Kottapalli
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2010 – 2019
- 2019
[j3]Mohamed Arafa
, Bahaa Fahim, Sailesh Kottapalli, Akhilesh Kumar, Lily Pao Looi, Sreenivas Mandava, Andy Rudoff, Ian M. Steiner, Bob Valentine, Geetha Vedaraman, Sujal Vora:
Cascade Lake: Next Generation Intel Xeon Scalable Processor. IEEE Micro 39(2): 29-36 (2019)- 2015
- [j2]Irma Esmer Papazian, Sailesh Kottapalli, Jeff Baxter, Jeff Chamberlain, Geetha Vedaraman, Brian Morris:
Ivy Bridge Server: A Converged Design. IEEE Micro 35(2): 16-25 (2015) - 2014
- [c5]Irma Esmer Papazian, Sailesh Kottapalli:
Ivybridge server architecture: A converged server. Hot Chips Symposium 2014: 1-29 - 2010
- [j1]Stefan Rusu, Simon M. Tam, Harry Muljono, Jason Stinson, David Ayers, Jonathan Chang, Raj Varada, Matt Ratta, Sailesh Kottapalli, Sujal Vora:
A 45 nm 8-Core Enterprise Xeon¯ Processor. IEEE J. Solid State Circuits 45(1): 7-14 (2010) - [c4]Dheemanth Nagaraj, Sailesh Kottapalli:
Westmere-EX: A 20 thread server CPU. Hot Chips Symposium 2010: 1-18
2000 – 2009
- 2009
- [c3]Stefan Rusu, Simon M. Tam, Harry Muljono, Jason Stinson, David Ayers, Jonathan Chang, Raj Varada, Matt Ratta, Sailesh Kottapalli, Sujal Vora:
Power reduction techniques for an 8-core xeon® processor. ESSCIRC 2009: 340-343 - [c2]Sailesh Kottapalli, Jeff Baxter:
Nahalem-EX CPU architecture. Hot Chips Symposium 2009: 1-19 - [c1]Stefan Rusu, Simon M. Tam, Harry Muljono, Jason Stinson, David Ayers, Jonathan Chang, Raj Varada, Matt Ratta, Sailesh Kottapalli:
A 45nm 8-core enterprise Xeon® processor. ISSCC 2009: 56-57
Coauthor Index
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