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ORCIDStefan Rusu
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2020 – today
- 2020
[j21]Mu-Shan Lin
, Tze-Chiang Huang, Chien-Chun Tsai, King-Ho Tam, Kenny Cheng-Hsiang Hsieh, Ching-Fang Chen, Wen-Hung Huang, Chi-Wei Hu, Yu-Chi Chen, Sandeep Kumar Goel, Chin-Ming Fu, Stefan Rusu, Chao-Chieh Li, Sheng-Yao Yang, Mei Wong, Shu-Chun Yang, Frank Lee:
A 7-nm 4-GHz Arm¹-Core-Based CoWoS¹ Chiplet Design for High-Performance Computing. IEEE J. Solid State Circuits 55(4): 956-966 (2020)
2010 – 2019
- 2019
- [j20]Ángel Rodríguez-Vázquez, Kaushik Sengupta, Stefan Rusu:
Guest Editorial: Special Section on the 48th European Solid-State Circuits Conference (ESSCIRC). IEEE J. Solid State Circuits 54(7): 1827-1829 (2019) - [j19]John Kubiatowicz, Stefan Rusu:
Hot Chips 30. IEEE Micro 39(2): 6-8 (2019) - [c14]Mu-Shan Lin, Tze-Chiang Huang, Chien-Chun Tsai, King-Ho Tam, Kenny Cheng-Hsiang Hsieh, Tom Chen, Wen-Hung Huang, Jack Hu, Yu-Chi Chen, Sandeep Kumar Goel, Chin-Ming Fu, Stefan Rusu, Chao-Chieh Li, Sheng-Yao Yang, Mei Wong, Shu-Chun Yang, Frank Lee:
A 7nm 4GHz Arm®-core-based CoWoS® Chiplet Design for High Performance Computing. VLSI Circuits 2019: 28- - 2016
- [j18]Andrea Mazzanti, Bram Nauta, Stefan Rusu:
Introduction to the Special Issue on the 41st European Solid-State Circuits Conference (ESSCIRC). IEEE J. Solid State Circuits 51(7): 1511-1513 (2016) - [c13]Stefan Rusu:
Welcome to 2016 Hot Chips. Hot Chips Symposium 2016: 1-10 - 2015
- [j17]Stefan Rusu, Harry Muljono, David Ayers, Simon M. Tam, Wei Chen, Aaron Martin, Shenggao Li, Sujal Vora, Raj Varada, Eddie Wang:
A 22 nm 15-Core Enterprise Xeon® Processor Family. IEEE J. Solid State Circuits 50(1): 35-48 (2015) - [j16]Stefan Rusu, Gregory Chen:
Introduction to the Special Section on the 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC). IEEE J. Solid State Circuits 50(11): 2472-2474 (2015) - 2014
- [j15]Yann Deval, Stefan Rusu:
Introduction to the Special Issue on the 39th European Solid-State Circuits Conference (ESSCIRC). IEEE J. Solid State Circuits 49(7): 1460-1462 (2014) - [c12]Stefan Rusu, Harry Muljono, David Ayers, Simon M. Tam, Wei Chen, Aaron Martin, Shenggao Li, Sujal Vora, Raj Varada, Eddie Wang:
5.4 Ivytown: A 22nm 15-core enterprise Xeon® processor family. ISSCC 2014: 102-103 - 2010
- [j14]Stefan Rusu, Simon M. Tam, Harry Muljono, Jason Stinson, David Ayers, Jonathan Chang, Raj Varada, Matt Ratta, Sailesh Kottapalli, Sujal Vora:
A 45 nm 8-Core Enterprise Xeon¯ Processor. IEEE J. Solid State Circuits 45(1): 7-14 (2010)
2000 – 2009
- 2009
- [j13]Kari A. I. Halonen, Kofi A. A. Makinwa, Stefan Rusu:
Introduction to the Special Issue on the 34th ESSCIRC. IEEE J. Solid State Circuits 44(7): 1859-1861 (2009) - [c11]Stefan Rusu, Simon M. Tam, Harry Muljono, Jason Stinson, David Ayers, Jonathan Chang, Raj Varada, Matt Ratta, Sailesh Kottapalli, Sujal Vora:
Power reduction techniques for an 8-core xeon® processor. ESSCIRC 2009: 340-343 - [c10]Stefan Rusu, Simon M. Tam, Harry Muljono, Jason Stinson, David Ayers, Jonathan Chang, Raj Varada, Matt Ratta, Sailesh Kottapalli:
A 45nm 8-core enterprise Xeon® processor. ISSCC 2009: 56-57 - [c9]Stefan Rusu:
Multi-domain processors. ISSCC 2009: 509 - 2008
- [j12]Andrea Baschirotto, Edoardo Charbon, Stefan Rusu:
Introduction to the Special Issue on the 33rd European Solid-State Circuits Conference (ESSCIRC 2007). IEEE J. Solid State Circuits 43(7): 1507-1510 (2008) - [c8]Ian Galton, Jonathan Audy, Vadim Ivanov, Stefan Rusu, Seth R. Sanders:
Short Course. ISSCC 2008: 648-649 - 2007
- [j11]Stefan Rusu, Simon M. Tam, Harry Muljono, David Ayers, Jonathan Chang, Brian S. Cherkauer, Jason Stinson, John Benoit, Raj Varada, Justin Leung, Rahul Dilip Limaye, Sujal Vora:
A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache. IEEE J. Solid State Circuits 42(1): 17-25 (2007) - [j10]Jonathan Chang, Ming Huang, Jonathan Shoemaker, John Benoit, Szu-Liang Chen, Wei Chen, Siufu Chiu, Raghuraman Ganesan, Gloria Leong, Venkata Lukka, Stefan Rusu, Durgesh Srivastava:
The 65-nm 16-MB Shared On-Die L3 Cache for the Dual-Core Intel Xeon Processor 7100 Series. IEEE J. Solid State Circuits 42(4): 846-852 (2007) - [j9]Andreas Kaiser, Stefan Rusu:
Introduction to the Special Issue on ESSCIRC 2006. IEEE J. Solid State Circuits 42(7): 1453-1454 (2007) - [c7]Stefan Rusu, Jim Warnock:
Microprocessors. ISSCC 2007: 94-95 - 2006
- [c6]Stefan Rusu, Simon M. Tam, Harry Muljono, David Ayers, Jonathan Chang:
A Dual-Core Multi-Threaded Xeon Processor with 16MB L3 Cache. ISSCC 2006: 315-324 - 2005
- [j8]Jonathan Chang, Stefan Rusu, Jonathan Shoemaker, Simon Tam, Ming Huang, Mizan Haque, Siufu Chiu, Kevin Truong, Mesbah Karim, Gloria Leong, Kiran Desai, Richard Goe, Sandhya Kulkarni:
A 130-nm triple-Vt 9-MB third-level on-die cache for the 1.7-GHz Itanium® 2 processor. IEEE J. Solid State Circuits 40(1): 195-203 (2005) - [j7]Rolf Koch, Stefan Rusu:
Introduction to the Special Issue on ESSCIRC'2004. IEEE J. Solid State Circuits 40(7): 1403-1405 (2005) - 2004
- [j6]Stefan Rusu, Harry Muljono, Brian S. Cherkauer:
Itanium 2 Processor 6M: Higher Frequency and Larger L3 Cache. IEEE Micro 24(2): 10-18 (2004) - [c5]Stefan Rusu:
Clock generation and distribution in high-performance processors. SoC 2004 - 2003
- [j5]Harry Muljono, Beom-Taek Lee, Yanmei (Kathy) Tian, Yanbin (Eddie) Wang, Mubeen Atha, Tiffany Huang, Mitsuhiro Adachi, Stefan Rusu:
A 400-MT/s 6.4-GB/s multiprocessor bus interface. IEEE J. Solid State Circuits 38(11): 1846-1856 (2003) - [j4]Stefan Rusu, Jason Stinson, Simon Tam, Justin Leung, Harry Muljono, Brian S. Cherkauer:
A 1.5-GHz 130-nm Itanium® 2 Processor with 6-MB on-die L3 cache. IEEE J. Solid State Circuits 38(11): 1887-1895 (2003) - [c4]Jason Stinson, Stefan Rusu:
A 1.5GHz third generation itanium® 2 processor. DAC 2003: 706-709 - 2002
- [j3]Christian C. Enz, Stefan Rusu:
Guest editorial. IEEE J. Solid State Circuits 37(7): 795-797 (2002) - [c3]Stefan Rusu, Manoj Sachdev, Christer Svensson, Bram Nauta:
Trends and Challenges in VLSI Technology Scaling towards 100nm (Tutorial Abstract). ASP-DAC/VLSI Design 2002: 16-17 - 2000
- [j2]Stefan Rusu, Gadi Singer:
The first IA-64 microprocessor. IEEE J. Solid State Circuits 35(11): 1539-1544 (2000) - [j1]Simon Tam, Stefan Rusu, Utpal Nagarji Desai, Robert Kim, Ji Zhang, Ian Young:
Clock generation and distribution for the first IA-64 microprocessor. IEEE J. Solid State Circuits 35(11): 1545-1552 (2000) - [c2]Utpal Desai, Simon M. Tam, Robert Kim, Ji Zhang, Stefan Rusu:
Itanium processor clock design. ISPD 2000: 94-98
1990 – 1999
- 1993
- [c1]Gregory Schulte, Peter Tong, Stefan Rusu, Stuart Taylor:
TONIC: A timing database for VLSI design. EURO-DAC 1993: 426-431
Coauthor Index
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