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2010 – 2019
- 2015
[j2]ByongChan Lim
, Ji-Eun Jang, James Mao, Jaeha Kim, Mark Horowitz:
Digital Analog Design: Enabling Mixed-Signal System Validation. IEEE Des. Test 32(1): 44-52 (2015)- [j1]Ji-Eun Jang, Jaeha Kim:
PPV-Based Modeling and Event-Driven Simulation of Injection-Locked Oscillators in SystemVerilog. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(8): 1908-1917 (2015) - 2014
- [c8]Jaeha Kim, Si-Jung Yang, Ji-Eun Jang:
PPV-based modeling and event-driven simulation of injection-locked oscillators in SystemVerilog. CICC 2014: 1-4 - 2013
- [c7]Ji-Eun Jang, Si-Jung Yang, Jaeha Kim:
Event-driven simulation of Volterra series models in SystemVerilog. CICC 2013: 1-4 - [c6]Ji-Eun Jang, Myeong-Jae Park, Jaeha Kim:
An event-driven simulation methodology for integrated switching power supplies in SystemVerilog. DAC 2013: 137:1-137:7 - 2012
- [c5]Ji-Eun Jang, Myeong-Jae Park, Dongyun Lee, Jaeha Kim:
True event-driven simulation of analog/mixed-signal behaviors in SystemVerilog: A decision-feedback equalizing (DFE) receiver example. CICC 2012: 1-4 - 2011
- [c4]Ji-Eun Jang:
Comparator-based switched-capacitor pipelined ADC with background offset calibration. ISCAS 2011: 253-256 - 2010
- [c3]Ji-Eun Jang, Yung-Kuang Miao, Yung-Pin Lee:
High-bandwidth power-scalable 10-bit pipelined ADC using bandwidth-reconfigurable operational amplifier. ISCAS 2010: 4029-4032 - [c2]Kuan-Yu Lin, Ji-Eun Jang, Ching-Hsuan Hsieh, Yung-Pin Lee:
A pipelined analog-to-digital converter using incomplete-settling-without-slewing technique. ISCAS 2010: 4037-4040
2000 – 2009
- 2009
- [c1]Dong Hun Shin, Ji-Eun Jang, Frank O'Mahony, C. Patrick Yue:
A 1-mW 12-Gb/s continuous-time adaptive passive equalizer in 90-nm CMOS. CICC 2009: 117-120
Coauthor Index
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