"A 2GHz-to-7.5GHz quadrature clock-generator using digital delay locked ..."

Amr Elshazly et al. (2014)

> Home

Details and statistics

DOI: 10.1109/VLSIC.2014.6858375

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-11

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/vlsic/ElshazlyBHYO14
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsic/ElshazlyBHYO14
Amr Elshazly, Ajay Balankutty, Yan-Yu Huang, Kai Yu, Frank O'Mahony:
A 2GHz-to-7.5GHz quadrature clock-generator using digital delay locked loops for multi-standard I/Os in 14nm CMOS. VLSIC 2014: 1-2

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.