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ORCIDThemistoklis Haniotakis
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2020 – today
- 2024
[i1]Sakib Mohammad, Themistoklis Haniotakis:
Design of a Reformed Array Logic Binary Multiplier for High-Speed Computations. CoRR abs/2409.16405 (2024)- 2020
- [c52]Konstantinos Poulos, Iraklis Anagnostopoulos, Themistoklis Haniotakis:
ARIAN: A Scalable Method for Adding aRbItrAry Numbers on Modern Processors. ISCAS 2020: 1-5 - [c51]Konstantinos Poulos, Themistoklis Haniotakis:
A Built In Test circuit for waveform classification at high frequencies. NATW 2020: 1-5
2010 – 2019
- 2019
- [j17]Raghava Katreepalli
, Themistoklis Haniotakis:
Power efficient synchronous counter design. Comput. Electr. Eng. 75: 288-300 (2019) - [j16]Theodoros Simopoulos, George Alexiou, Themistoklis Haniotakis:
Implementation Guidelines of WDSRAM and Comparison with Typical SRAM Using Nanoscale Hierarchical Implementation Model. J. Circuits Syst. Comput. 28(Supplement-1): 1940008:1-1940008:14 (2019) - 2018
- [j15]Seyed Nima Mozaffari, Spyros Tragoudas, Themistoklis Haniotakis:
A Generalized Approach to Implement Efficient CMOS-Based Threshold Logic Functions. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(3): 946-959 (2018) - [c50]Theodoros Simopoulos, Themistoklis Haniotakis, George Alexiou:
A 1Kx32 bit WDSRAM page with rapid write access. DTIS 2018: 1-2 - 2017
- [j14]Seyed Nima Mozaffari, Spyros Tragoudas, Themistoklis Haniotakis:
More Efficient Testing of Metal-Oxide Memristor-Based Memory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(6): 1018-1029 (2017) - [j13]Chandra Babu Dara, Themistoklis Haniotakis, Spyros Tragoudas:
Delay Analysis for Current Mode Threshold Logic Gate Designs. IEEE Trans. Very Large Scale Integr. Syst. 25(3): 1063-1071 (2017) - [c49]Seyed Nima Mozaffari, Spyros Tragoudas, Themistoklis Haniotakis:
A new method to identify threshold logic functions. DATE 2017: 934-937 - [c48]Seyed Nima Mozaffari, Spyros Tragoudas, Themistoklis Haniotakis:
Reducing power, area, and delay of threshold logic gates considering non-integer weights. ISCAS 2017: 1-4 - [c47]Raghava Katreepalli, Themistoklis Haniotakis:
High Speed Power Efficient Carry Select Adder Design. ISVLSI 2017: 32-37 - [c46]Konstantinos Poulos, Jayasurya Kuchi, Themistoklis Haniotakis:
An enhanced approach to reduce test application time through limited shift operations in scan chains. NATW 2017: 1-4 - 2016
- [j12]Ashok Kumar Palaniswamy, Spyros Tragoudas, Themistoklis Haniotakis:
ATPG for Delay Defects in Current Mode Threshold Logic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(11): 1903-1913 (2016) - [c45]Wisam Aljubouri, Spyros Tragoudas, Themistoklis Haniotakis:
Identification of delay defects on embedded paths using one current sensor. DTIS 2016: 1-4 - [c44]Raghava Katreepalli, Hemanth Chemanchula, Themistoklis Haniotakis, Yiorgos Tsiatouhas:
Low-Power and High Performance Sinusoidal Clocked Dynamic Circuit Design. ISVLSI 2016: 367-372 - 2015
- [j11]Sotirios Matakias, Yiorgos Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis:
A current monitoring technique for IDDQ testing in digital integrated circuits. Integr. 50: 48-60 (2015) - [c43]Seyed Nima Mozaffari, Spyros Tragoudas, Themistoklis Haniotakis:
Fast march tests for defects in resistive memory. NANOARCH 2015: 88-93 - 2014
- [c42]Wisam Aljubouri, Ahish Mysore Somashekar, Themistoklis Haniotakis, Spyros Tragoudas:
Diagnosis of segment delay defects with current sensing. DFT 2014: 122-127 - [c41]Ashok Kumar Palaniswamy, Spyros Tragoudas, Themistoklis Haniotakis:
ATPG for transition faults of pipelined threshold logic circuits. DTIS 2014: 1-5 - [c40]Theodoros Simopoulos, Themistoklis Haniotakis, George Alexiou:
Implementation of a Low Leakage Standard Cell Library based on materials from UMC 65nm technology. Panhellenic Conference on Informatics 2014: 36:1-36:2 - 2013
- [c39]Chandra Babu Dara, Themistoklis Haniotakis, Spyros Tragoudas:
Low power and high speed current-mode memristor-based TLGs. DFTS 2013: 89-94 - 2012
- [j10]Khadija Jirari Stewart, Themistoklis Haniotakis, Spyros Tragoudas:
Securing sensor networks: A novel approach that combines encoding, uncorrelation and node disjoint transmission. Ad Hoc Networks 10(3): 328-338 (2012) - [c38]Chandra Babu Dara, Themistoklis Haniotakis, Spyros Tragoudas:
Delay Analysis for an N-Input Current Mode Threshold Logic Gate. ISVLSI 2012: 344-349 - 2011
- [c37]Chandra Babu Dara, Spyros Tragoudas, Themistoklis Haniotakis:
A Metric for Weight Assignment to Optimize the Performance of MOBILE Threshold Logic Gate. DFT 2011: 131-138 - 2010
- [j9]Michael N. Skoufis, Kedar Karmarkar, Spyros Tragoudas, Themistoklis Haniotakis:
A Data Capturing Method for Buses on Chip. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(7): 1631-1641 (2010) - [c36]Themistoklis Haniotakis, Zaher Owda, Yiorgos Tsiatouhas:
Memory-Less Pipeline Dynamic Circuit Design Technique. ISVLSI 2010: 201-205
2000 – 2009
- 2008
- [j8]Sotirios Matakias, Yiorgos Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni:
A Current Mode, Parallel, Two-Rail Code Checker. IEEE Trans. Computers 57(8): 1032-1045 (2008) - [c35]Michael N. Skoufis, Kedar Karmarkar, Themistoklis Haniotakis, Spyros Tragoudas:
A High-Performance Bus Architecture for Strongly Coupled Interconnects. ISQED 2008: 407-410 - 2007
- [j7]Themistoklis Haniotakis, Y. Tsiatouhas, Dimitris Nikolos, Costas Efstathiou:
Testable Designs of Multiple Precharged Domino Circuits. IEEE Trans. Very Large Scale Integr. Syst. 15(4): 461-465 (2007) - [j6]Dimitrios Kagaris, Themistoklis Haniotakis:
A Methodology for Transistor-Efficient Supergate Design. IEEE Trans. Very Large Scale Integr. Syst. 15(4): 488-492 (2007) - [c34]Michael N. Skoufis, Haibo Wang, Themistoklis Haniotakis, Spyros Tragoudas:
Glitch Control with Dynamic Receiver Threshold Adjustment. ISQED 2007: 410-415 - [c33]Dimitri Kagaris, Themistoklis Haniotakis:
Transistor-Level Synthesis for Low-Power Applications. ISQED 2007: 607-612 - 2006
- [j5]Konstantinos Limniotis, Yiorgos Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni:
A Design Technique for Energy Reduction in NORA CMOS Logic. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(12): 2647-2655 (2006) - [c32]Andreas Floros, Yiorgos Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis:
A Pipeline Architecture Incorporating a Low-Cost Error Detection and Correction Mechanism. ICECS 2006: 692-695 - [c31]Edward Flanigan, Themistoklis Haniotakis, Spyros Tragoudas:
An Improved Method for Identifying Linear Dependencies in Path Delay Faults. ISQED 2006: 457-462 - [c30]Dimitri Kagaris, Themistoklis Haniotakis:
Transistor-Level Optimization of Supergates. ISQED 2006: 682-690 - 2005
- [c29]Sotirios Matakias, Yiorgos Tsiatouhas, Angela Arapoyanni, Th. Haniotakis, Guillaume Prenat, Salvador Mir:
A built-in IDDQ testing circuit. ESSCIRC 2005: 471-474 - [c28]Khadija Jirari Stewart, Themistoklis Haniotakis, Spyros Tragoudas:
A security protocol for sensor networks. GLOBECOM 2005: 5 - [c27]Sotirios Matakias, Yiorgos Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis:
An embedded IDDQ testing circuit and technique. ICECS 2005: 1-4 - [c26]Sotirios Matakias, Y. Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, Aristides Efthymiou:
Fast, Parallel Two-Rail Code Checker with Enhanced Testability. IOLTS 2005: 149-156 - [c25]Khadija Jirari Stewart, Themistoklis Haniotakis, Spyros Tragoudas:
Design and Evaluation of a Security Scheme for Sensor Networks. ISQED 2005: 197-201 - [c24]Themistoklis Haniotakis, Spyros Tragoudas, G. Pani:
Reduced Test Application Time Based on Reachability Analysis. ISQED 2005: 232-237 - [c23]A. Rao, Th. Haniotakis, Y. Tsiatouhas, H. Djemil:
The Use of Pre-Evaluation Phase in Dynamic CMOS Logic. ISVLSI 2005: 270-271 - 2004
- [j4]Sotirios Matakias, Y. Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis:
A Circuit for Concurrent Detection of Soft and Timing Errors in Digital CMOS ICs. J. Electron. Test. 20(5): 523-531 (2004) - [j3]Maria K. Michael, Themistoklis Haniotakis, Spyros Tragoudas:
A unified framework for generating all propagation functions for logic errors and events. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(6): 980-986 (2004) - [c22]Themistoklis Haniotakis, Spyros Tragoudas, Constantinos Kalapodas:
Security enhancement through multiple path transmission in ad hoc networks. ICC 2004: 4187-4191 - [c21]A. Rao, Th. Haniotakis, Y. Tsiatouhas, V. Kaky:
A New Dynamic Circuit Design Technique for High Performance TSC Checker Implementations. IOLTS 2004: 52-57 - [c20]Sotirios Matakias, Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni:
Ultra Fast and Low Cost Parallel Two-Rail Code Checker Targeting High Fan-In Applications . ISVLSI 2004: 293-296 - 2003
- [c19]Yiorgos Tsiatouhas, Konstantinos Limniotis, Angela Arapoyanni, Themistoklis Haniotakis:
A low power NORA circuit design technique based on charge recycling. ICECS 2003: 224-227 - [c18]Y. Tsiatouhas, Sotirios Matakias, Angela Arapoyanni, Th. Haniotakis:
A Sense Amplifier Based Circuit for Concurrent Detection of Soft and Timing Errors in CMOS ICs. IOLTS 2003: 12-16 - [c17]Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni:
An Embedded IDDQ Testing Architecture and Technique. ISQED 2003: 442-445 - 2002
- [j2]Y. Tsiatouhas, Yiannis Moisiadis, Th. Haniotakis, Dimitris Nikolos, Angela Arapoyanni:
A new technique for IDDQ testing in nanometer technologies. Integr. 31(2): 183-194 (2002) - [c16]Y. Tsiatouhas, Angela Arapoyanni, Dimitris Nikolos, Th. Haniotakis:
A Hierarchical Architecture for Concurrent Soft Error Detection Based on Current Sensing. IOLTW 2002: 56-60 - [c15]A. Chrisanthopoulos, Y. Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis:
SRAM oriented memory sense amplifier design in 0.18 μm CMOS technology. ISCAS (5) 2002: 145-148 - [c14]Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos, Angela Arapoyanni:
Extending the Viability of IDDQ Testing in the Deep Submicron Era. ISQED 2002: 100-105 - 2001
- [c13]A. Chrisanthopoulos, Th. Haniotakis, Y. Tsiatouhas, Angela Arapoyanni:
New test pattern generation units for NPSF oriented memory built-in self test. ICECS 2001: 749-752 - [c12]Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos, Costas Efstathiou:
Concurrent Detection of Soft Errors Based on Current Monitoring. IOLTW 2001: 106-110 - 2000
- [c11]Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni, Dimitris Nikolos:
A Versatile Built-In Self-Test Scheme for Delay Fault Testing. DATE 2000: 756 - [c10]Y. Tsiatouhas, A. Chrisanthopoulos, George Kamoulakos, Th. Haniotakis:
New memory sense amplifier designs in CMOS technology. ICECS 2000: 19-22 - [c9]Dionisis Skias, Th. Haniotakis, Y. Tsiatouhas, Angela Arapoyanni:
A state assignment algorithm for finite state machines. ICECS 2000: 823-826 - [c8]Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos:
A Compact Built-In Current Sensor for IDDQ Testing. IOLTW 2000: 95-99 - [c7]Th. Haniotakis, Y. Tsiatouhas, Dimitris Nikolos, Costas Efstathiou:
On Testability of Multiple Precharged Domino Logic. ISQED 2000: 299-304
1990 – 1999
- 1999
- [c6]Dimitris Nikolos, Haridimos T. Vergos, Th. Haniotakis, Y. Tsiatouhas:
Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks. DATE 1999: 112-116 - [c5]Y. Tsiatouhas, Th. Haniotakis:
A Zero Aliasing Built-In Self Test Technique for Delay Fault Testing. DFT 1999: 95-100 - [c4]Haridimos T. Vergos, Dimitris Nikolos, Y. Tsiatouhas, Th. Haniotakis, Michael Nicolaidis:
On Path Delay Fault Testing of Multiplexer - Based Shifters. Great Lakes Symposium on VLSI 1999: 20-23 - [c3]Th. Haniotakis, Y. Tsiatouhas, Angela Arapoyanni:
Novel domino logic designs. ICECS 1999: 213-216 - 1998
- [c2]Th. Haniotakis, Dimitris Nikolos, Y. Tsiatouhas:
C-Testable One-Dimensional ILAs with Respect to Path Delay Faults: Theory and Applications. DFT 1998: 155-163 - 1995
- [j1]Th. Haniotakis, Antonis M. Paschalis, Dimitris Nikolos:
Efficient Totally Self-Checking Checkers for a Class of Borden Codes. IEEE Trans. Computers 44(11): 1318-1322 (1995) - [c1]Ioannis Voyiatzis, Dimitris Nikolos, Antonis M. Paschalis, Constantinos Halatsis, Th. Haniotakis:
An efficient comparative concurrent Built-In Self-Test technique. Asian Test Symposium 1995: 309-315
Coauthor Index
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