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ORCID10th IOLTS 2004: Funchal, Madeira Island, Portugal
- 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 12-14 July 2004, Funchal, Madeira Island, Portugal. IEEE Computer Society 2004, ISBN 0-7695-2180-0
Opening Session-Keynote Talk
- V. Agarwal:
A Pragmatic Approach to On-Line Testing. 1-4
Session 1: Timing and Transient Faults
- Daniel Barros Jr., Fabian Vargas, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira:
Modeling and Simulation of Time Domain Faults in Digital Systems. 5-10 - Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh:
Sizing CMOS Circuits for Increased Transient Error Tolerance. 11-16 - José Manuel Cazeaux, Martin Omaña, Cecilia Metra:
Low-Area On-Chip Circuit for Jitter Measurement in a Phase-Locked Loop. 17-24
Session 2: Self Testing and Self Checking Circuits
- Valerij V. Saposhnikov, Vladimir V. Saposhnikov, Andrej A. Morosov, Michael Gössel:
Necessary and Sufficient Conditions for the Existence of Totally Self-Checking Circuits. 25-30 - Vitalij Ocheretnij, Daniel Marienfeld, Egor S. Sogomonyan, Michael Gössel:
Self-Checking Code-Disjoint Carry-Select Adder with Low Area Overhead by Use of Add1-Circuits. 31-36 - Claudia Kretzschmar, Christian Galke, Heinrich Theodor Vierhaus:
A Hierarchical Self Test Scheme for SoCs. 37-44
Session 3: Checker and Voter Design
- Steffen Tarnick:
Single-Output Embedded Checkers for Systematic Unordered Codes. 45-51 - A. Rao, Th. Haniotakis, Y. Tsiatouhas, V. Kaky:
A New Dynamic Circuit Design Technique for High Performance TSC Checker Implementations. 52-57 - José Manuel Cazeaux, Daniele Rossi, Cecilia Metra:
New High Speed CMOS Self-Checking Voter. 58-66
Session 4: Concurrent Error Detection
- Andrzej Krasniewski:
Concurrent Error Detection in Sequential Circuits Implemented Using FPGAs with Embedded Memory Blocks. 67-72 - Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin:
Low Cost On-Line Testing of RF Circuits. 73-78 - Letícia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Vargas, Massimo Violante:
Hybrid Soft Error Detection by Means of Infrastructure IP Cores. 79-88
Panel Session 1: On Emerging Field Reliability and Dependability Challenge
Session 5: Microprocessor On-Line Testing
- Peter D. Hyde, G. Russell:
A Comparative Study of the Design of Synchronous and Asynchronous Self-Checking RISC Processors. 89-94 - Eric F. Weglarz, Kewal K. Saluja, T. M. Mak:
Testing of Hard Faults in Simultaneous Multithreaded Processors. 95-100 - Hamid R. Zarandi, Seyed Ghassem Miremadi, Hamid Sarbazi-Azad:
Fault Detection Enhancement in Cache Memories Using a High Performance Placement Algorithm. 101-108
Session 6: On-Line Testing Evaluation
- Mario García-Valderas, Celia López-Ongil, Marta Portela-García, Luis Entrena:
Transient Fault Emulation of Hardened Circuits in FPGA Platforms. 109-114 - Paolo Bernardi, Matteo Sonza Reorda, Luca Sterpone, Massimo Violante:
On the Evaluation of SEU Sensitiveness in SRAM-Based FPGAs. 115-120 - Yannick Monnet, Marc Renaudin, Régis Leveugle:
Asynchronous Circuits Sensitivity to Fault Injection. 121-128
Session 7: Error Correcting Code Based Fault Tolerance
- Amine M'sir, Fabrice Monteiro, Abbas Dandache, Bernard Lepley:
Designing a High Speed Decoder for Cyclic Codes. 129-134 - Daniele Rossi, A. Muccio, André K. Nieuwland, Atul Katoch, Cecilia Metra:
Impact of ECCs on Simultaneously Switching Output Noise for On-Chip Busses of High Reliability Systems. 135-140 - Gian Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano:
A Signed Digit Adder with Error Correction and Graceful Degradation Capabilities. 141-148
Session 8: Reconfiguration, Repair, and Reuse for Fault Tolerance
- Amit Agarwal, Bipul Chandra Paul, Kaushik Roy:
A Novel Fault Tolerant Cache to Improve Yield in Nanometer Technologies. 149-154 - Miguel Garvie, Adrian Thompson:
Scrubbing Away Transients and Jiggling Around the Permanent: Long Survival of FPGA Systems Through Evolutionary Self-Repair. 155-160 - Cecilia Metra, A. Ferrari, Martin Omaña, Andrea Pagni:
Hardware Reconfiguration Scheme for High Availability Systems. 161-166 - Michele Portolan, Régis Leveugle:
Operating System Function Reuse to Achieve Low-Cost Fault Tolerance. 167-174
Session 9: Posters
- Eberhard Böhl, Elmar Dilger, M. Böhl:
A New Code with Reduced EMI and Partial EC Possibilities. 175 - Thomas O'Shea, Ian Andrew Grout:
A Matlab Based On-Chip Signal Generation and Analysis Environment for Mixed Signal Circuits. 176 - André K. Nieuwland, Patrick Gindner:
Automated Logic SER Analysis and On-Line SER reduction. 177 - Jose Miguel Vieira dos Santos:
On the Design of Long-Life Reliable Systems for Ground-Based Applications. 178 - Rodrigo Picos, Miquel Roca, Eugeni Isern, Sebastià A. Bota, Eugenio García:
On-line Monitoring Capabilities of Oscillation Test Techniques: Results Demonstration in an OTA. 179 - Carlos Arthur Lang Lisbôa, Luigi Carro:
An Intrinsically Robust Technique for Fault Tolerance under Multiple Upsets. 180 - Petr Fiser, Hana Kubátová:
Survey of the Algorithms in the Column-Matching BIST Method. 181 - Debjyoti Ghosh, Swarup Bhunia, Kaushik Roy:
A Technique to Reduce Power and Test Application Time in BIST. 182-183 - Santosh Biswas, Siddhartha Mukhopadhyay, Amit Patra:
Optimization of the Theory of FDD of DES for Alleviation of the State Explosion Problem and Development of CAD Tools for On-line Testing of Digital VLSI Circuits. 184-
Session 10: Built In Self Test
- Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell:
BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs. 187-192 - P. Karpodinis, Dimitri Kagaris, Dimitris Nikolos:
Accumulator based Test-per-Scan BIST. 193-198 - Bartomeu Alorda, Vicent Canals, Ivan de Paúl, Jaume Segura:
A BIST-based Charge Analysis for Embedded Memories. 199-206
Session 11: Safety and Security
- Nikolaos G. Bartzoudis, Alexandros G. Fragkiadakis, David J. Parish, José Luis Núñez:
A System for Fault Detection and Reconfiguration of Hardware Based Active Networks. 207-213 - Elmar Dilger, Roland Karrelmeyer, Bernd Straube:
Fault Tolerant Mechatronics. 214-218 - David Hély, Marie-Lise Flottes, Frédéric Bancel, Bruno Rouzeyre, Nicolas Bérard, Michel Renovell:
Scan Design and Secure Chip. 219-226
Session 12: Dependability Evaluation
- Abdelaziz Ammari, K. Hadjiat, Régis Leveugle:
On Combining Fault Classification and Error Propagation Analysis in RT-Level Dependability Evaluation. 227-232 - Bogdan Nicolescu, Yvon Savaria, Raoul Velazco:
Performance Evaluation and Failure Rate Prediction for the Soft Implemented Error Detection Technique. 233-238 - Amir Rajabzadeh, Seyed Ghassem Miremadi, Mirzad Mohandespour:
Experimental Evaluation of Master/Checker Architecture Using Power Supply- and Software-Based Fault Injection. 239-246
Panel Session 2: Reliability Implications of Statistical Design
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