"ATPG for Delay Defects in Current Mode Threshold Logic Circuits."

Ashok Kumar Palaniswamy, Spyros Tragoudas, Themistoklis Haniotakis (2016)

> Home

Details and statistics

DOI: 10.1109/TCAD.2016.2533863

access: closed

type: Journal Article

metadata version: 2020-09-24

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tcad/PalaniswamyTH16
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tcad/PalaniswamyTH16
Ashok Kumar Palaniswamy, Spyros Tragoudas, Themistoklis Haniotakis:
ATPG for Delay Defects in Current Mode Threshold Logic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(11): 1903-1913 (2016)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.